netdev - Re: [PATCH V3 net-next 1/8] net: ena: avoid unnecessary rearming of interrupt vector when busy-polling

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Message-Id: <20200717.125227.55028219209538840.davem@davemloft.net>
Date:   Fri, 17 Jul 2020 12:52:27 -0700 (PDT)
From:   David Miller <davem@...emloft.net>
To:     akiyano@...zon.com
Cc:     netdev@...r.kernel.org, dwmw@...zon.com, zorik@...zon.com,
        matua@...zon.com, saeedb@...zon.com, msw@...zon.com,
        aliguori@...zon.com, nafea@...zon.com, gtzalik@...zon.com,
        netanel@...zon.com, alisaidi@...zon.com, benh@...zon.com,
        ndagan@...zon.com, shayagr@...zon.com, sameehj@...zon.com,
        eric.dumazet@...il.com
Subject: Re: [PATCH V3 net-next 1/8] net: ena: avoid unnecessary rearming
 of interrupt vector when busy-polling

From: <akiyano@...zon.com>
Date: Thu, 16 Jul 2020 21:10:03 +0300

> To the best of my knowledge this assumption holds for ARM64 and x86_64
> architecture which use a MESI like cache coherency model.

Use the well defined kernel memory model correctly please.

This is no place for architectural assumptions.  The memory model of
the kernel defines the rules, and in what locations various memory
barriers are required for correct operation.

Thank you.