netdev - Re: [PATCH V3 net-next 1/8] net: ena: avoid unnecessary rearming of interrupt vector when busy-polling

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Message-ID: <097BE2F6-0737-4658-B2EA-4760643BCBB1@amazon.com>
Date:   Fri, 17 Jul 2020 20:28:18 +0000
From:   "Bshara, Nafea" <nafea@...zon.com>
To:     David Miller <davem@...emloft.net>,
        "Kiyanovski, Arthur" <akiyano@...zon.com>
CC:     "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "Woodhouse, David" <dwmw@...zon.co.uk>,
        "Machulsky, Zorik" <zorik@...zon.com>,
        "Matushevsky, Alexander" <matua@...zon.com>,
        "Bshara, Saeed" <saeedb@...zon.com>,
        "Wilson, Matt" <msw@...zon.com>,
        "Liguori, Anthony" <aliguori@...zon.com>,
        "Tzalik, Guy" <gtzalik@...zon.com>,
        "Belgazal, Netanel" <netanel@...zon.com>,
        "Saidi, Ali" <alisaidi@...zon.com>,
        "Herrenschmidt, Benjamin" <benh@...zon.com>,
        "Dagan, Noam" <ndagan@...zon.com>,
        "Agroskin, Shay" <shayagr@...zon.com>,
        "Jubran, Samih" <sameehj@...zon.com>,
        "eric.dumazet@...il.com" <eric.dumazet@...il.com>
Subject: Re: [PATCH V3 net-next 1/8] net: ena: avoid unnecessary rearming of
 interrupt vector when busy-polling



On 7/17/20, 12:53 PM, "David Miller" <davem@...emloft.net> wrote:

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    From: <akiyano@...zon.com>
    Date: Thu, 16 Jul 2020 21:10:03 +0300

    > To the best of my knowledge this assumption holds for ARM64 and x86_64
    > architecture which use a MESI like cache coherency model.

    Use the well defined kernel memory model correctly please.

    This is no place for architectural assumptions.  The memory model of
    the kernel defines the rules, and in what locations various memory
    barriers are required for correct operation.

    Thank you.

True and we will add smp_rmb()
And I wouldn’t worry about the perf hit here, both x86 and modern arm v8 (specifically the Graviton2 that uses ENA) are pretty efficient and close enough to no-op