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Date: Thu, 3 Sep 2020 03:24:14 +0200 From: Andrew Lunn <andrew@...n.ch> To: Russell King <rmk+kernel@...linux.org.uk> Cc: Alexandre Belloni <alexandre.belloni@...tlin.com>, Antoine Tenart <antoine.tenart@...tlin.com>, Richard Cochran <richardcochran@...il.com>, Matteo Croce <mcroce@...hat.com>, Andre Przywara <andre.przywara@....com>, Sven Auhagen <sven.auhagen@...eatech.de>, "David S. Miller" <davem@...emloft.net>, Jakub Kicinski <kuba@...nel.org>, netdev@...r.kernel.org Subject: Re: [PATCH net-next 3/7] net: mvpp2: check first level interrupt status registers On Wed, Sep 02, 2020 at 05:11:46PM +0100, Russell King wrote: > Check the first level interrupt status registers to determine how to > further process the port interrupt. We will need this to know whether > to invoke the link status processing and/or the PTP processing for > both XLG and GMAC. As i said, i don't know this driver. Does the hardware actually have two MAC hardware blocks? One for 10Mbs->1G, and a second for > 1G? The comments and code seem to fit, so: Reviewed-by: Andrew Lunn <andrew@...n.ch> Andrew
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