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Date: Mon, 28 Sep 2020 07:58:41 +0000 From: Joakim Zhang <qiangqing.zhang@....com> To: Marc Kleine-Budde <mkl@...gutronix.de>, "linux-can@...r.kernel.org" <linux-can@...r.kernel.org>, Pankaj Bansal <pankaj.bansal@....com> CC: dl-linux-imx <linux-imx@....com>, "netdev@...r.kernel.org" <netdev@...r.kernel.org> Subject: RE: [PATCH linux-can-next/flexcan 1/4] can: flexcan: initialize all flexcan memory for ECC function > -----Original Message----- > From: Marc Kleine-Budde <mkl@...gutronix.de> > Sent: 2020年9月28日 15:01 > To: Joakim Zhang <qiangqing.zhang@....com>; linux-can@...r.kernel.org; > Pankaj Bansal <pankaj.bansal@....com> > Cc: dl-linux-imx <linux-imx@....com>; netdev@...r.kernel.org > Subject: Re: [PATCH linux-can-next/flexcan 1/4] can: flexcan: initialize all flexcan > memory for ECC function > > On 9/28/20 4:27 AM, Joakim Zhang wrote: > >> If it's OK on all SoCs to initialize the complete RAM area, just do > >> it. Then we can get rid of the proposed struct at all. > > > > Should be OK according to IP guys feedbacks. > > Good! > > > static const struct flexcan_devtype_data fsl_vf610_devtype_data = { > > .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | > FLEXCAN_QUIRK_ENABLE_EACEN_RRS | > > FLEXCAN_QUIRK_DISABLE_MECR | > FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | > > FLEXCAN_QUIRK_BROKEN_PERR_STATE, > > }; > > > > static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = { > > .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | > FLEXCAN_QUIRK_ENABLE_EACEN_RRS | > > FLEXCAN_QUIRK_DISABLE_MECR | > FLEXCAN_QUIRK_BROKEN_PERR_STATE | > > FLEXCAN_QUIRK_USE_OFF_TIMESTAMP, > > }; > > > > static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = { > > .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | > FLEXCAN_QUIRK_ENABLE_EACEN_RRS | > > FLEXCAN_QUIRK_DISABLE_MECR | > FLEXCAN_QUIRK_BROKEN_PERR_STATE | > > FLEXCAN_QUIRK_USE_OFF_TIMESTAMP | > FLEXCAN_QUIRK_SUPPORT_FD, }; > > > I am checking layerscape's CAN section: > > > > There is no ECC section in LS1021A > > https://www.nxp.com/products/processors-and-microcontrollers/arm-proce > > ssors/layerscape-multicore-processors/layerscape-1021a-dual-core-commu > > nications-processor-with-lcd-controller:LS1021A?tab=Documentation_Tab > > Hmmm, why does the LS1021A have "FLEXCAN_QUIRK_DISABLE_MECR"? The > bits in the > ctrl2 and the mecr register itself used in the quirk are marked as reserved in > this datasheet.... > > Can @Pankaj Bansal clarify this? > > > ECC section in LX2160A, also contains the same NOTE as i.MX8MP. > > https://www.nxp.com/products/processors-and-microcontrollers/arm-proce > > ssors/layerscape-multicore-processors/layerscape-lx2160a-multicore-com > > munications-processor:LX2160A?tab=Documentation_Tab > > > Hi @Pankaj Bansal, could you please also have a check? > Can someone check the vf610, too? I check the VF610 RM just now, indeed it has ECC feature, there is also a NOTE in "12.1.4.13 Detection and Correction of Memory Errors" section: All FlexCAN memory must be initialized before starting its operation in order to have the parity bits in memory properly updated. The WRMFRZ bit in Control 2 Register (CTRL2) grants write access to all memory positions from 0x080 to 0xADF. Best Regards, Joakim Zhang > regards, > Marc > > -- > Pengutronix e.K. | Marc Kleine-Budde | > Embedded Linux | https://www.pengutronix.de | > Vertretung West/Dortmund | Phone: +49-231-2826-924 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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