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Date:   Wed, 7 Oct 2020 10:23:14 +0200
From:   Marek Vasut <>
To:     Marco Felsch <>,
        Florian Fainelli <>
Cc:     Oleksij Rempel <>,
        Andrew Lunn <>,,
        Russell King <>,,,, David Jander <>
Subject: Re: PHY reset question

On 10/7/20 10:14 AM, Marco Felsch wrote:
> Hi Marek,



> On 20-10-06 14:11, Florian Fainelli wrote:
>> On 10/6/2020 1:24 PM, Marek Vasut wrote:
> ...
>>> If this happens on MX6 with FEC, can you please try these two patches?
>> Your patches are not scaling across multiple Ethernet MAC drivers
>> unfortunately, so I am not sure this should be even remotely considered a
>> viable solution.
> Recently I added clk support for the smcs driver [1] and dropped the
> PHY_RST_AFTER_CLK_EN flag for LAN8710/20 devices because I had the same
> issues. Hope this will help you too.
> [1]

I feel this might be starting to go a bit off-topic here, but isn't the
last patch 5/5 breaking existing setups ? The LAN8710 surely does need
clock enabled before the reset line is toggled.

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