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Date:   Wed, 7 Oct 2020 10:23:14 +0200
From:   Marek Vasut <marex@...x.de>
To:     Marco Felsch <m.felsch@...gutronix.de>,
        Florian Fainelli <f.fainelli@...il.com>
Cc:     Oleksij Rempel <o.rempel@...gutronix.de>,
        Andrew Lunn <andrew@...n.ch>, netdev@...r.kernel.org,
        Russell King <linux@...linux.org.uk>,
        linux-kernel@...r.kernel.org, mkl@...gutronix.de,
        kernel@...gutronix.de, David Jander <david@...tonic.nl>
Subject: Re: PHY reset question

On 10/7/20 10:14 AM, Marco Felsch wrote:
> Hi Marek,

Hi,

[...]

> On 20-10-06 14:11, Florian Fainelli wrote:
>> On 10/6/2020 1:24 PM, Marek Vasut wrote:
> 
> ...
> 
>>> If this happens on MX6 with FEC, can you please try these two patches?
>>>
>>> https://patchwork.ozlabs.org/project/netdev/patch/20201006135253.97395-1-marex@denx.de/
>>>
>>> https://patchwork.ozlabs.org/project/netdev/patch/20201006202029.254212-1-marex@denx.de/
>>
>> Your patches are not scaling across multiple Ethernet MAC drivers
>> unfortunately, so I am not sure this should be even remotely considered a
>> viable solution.
> 
> Recently I added clk support for the smcs driver [1] and dropped the
> PHY_RST_AFTER_CLK_EN flag for LAN8710/20 devices because I had the same
> issues. Hope this will help you too.
> 
> [1] https://www.spinics.net/lists/netdev/msg682080.html

I feel this might be starting to go a bit off-topic here, but isn't the
last patch 5/5 breaking existing setups ? The LAN8710 surely does need
clock enabled before the reset line is toggled.

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