netdev - Re: [PATCH net 1/4] ptp: ptp_idt82p33: update to support adjphase

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Message-ID: <20201017103354.GA4607@amd>
Date:   Sat, 17 Oct 2020 12:33:54 +0200
From:   Pavel Machek <pavel@...x.de>
To:     Min Li <min.li.xe@...esas.com>
Cc:     "richardcochran@...il.com" <richardcochran@...il.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH net 1/4] ptp: ptp_idt82p33: update to support adjphase

Hi!

> +static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 
> +offsetNs) {

adj_write_phase?

> +	struct idt82p33_channel *channel =
> +		container_of(ptp, struct idt82p33_channel, caps);
> +	struct idt82p33 *idt82p33 = channel->idt82p33;
> +	s64 offsetInFs;
> +	s64 offsetRegVal;
> +	u8 val[4] = {0};
> +	int err;
> +
> +	offsetInFs = (s64)(-offsetNs) * 1000000;
> +
> +	if (offsetInFs > WRITE_PHASE_OFFSET_LIMIT)
> +		offsetInFs = WRITE_PHASE_OFFSET_LIMIT;
> +	else if (offsetInFs < -WRITE_PHASE_OFFSET_LIMIT)
> +		offsetInFs = -WRITE_PHASE_OFFSET_LIMIT;

I'm sure we have macro for this.

> +	/* Convert from phaseOffsetInFs to register value */
> +	offsetRegVal = ((offsetInFs * 1000) / IDT_T0DPLL_PHASE_RESOL);
> +
> +	val[0] = offsetRegVal & 0xFF;
> +	val[1] = (offsetRegVal >> 8) & 0xFF;
> +	val[2] = (offsetRegVal >> 16) & 0xFF;
> +	val[3] = (offsetRegVal >> 24) & 0x1F;
> +	val[3] |= PH_OFFSET_EN;

ThisIsReally far away from usual coding style.

Best regards,
								Pavel
-- 
http://www.livejournal.com/~pavelmachek

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