netdev - Re: [EXTERNAL] Re: [PATCH net 0/4] Restore and fix PHY reset for SMSC LAN8720

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Date:   Wed, 4 Nov 2020 14:11:04 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     "Badel, Laurent" <LaurentBadel@...on.com>
Cc:     Marco Felsch <m.felsch@...gutronix.de>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "fugang.duan@....com" <fugang.duan@....com>,
        "kuba@...nel.org" <kuba@...nel.org>,
        Heiner Kallweit <hkallweit1@...il.com>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
        "lgirdwood@...il.com" <lgirdwood@...il.com>,
        "broonie@...nel.org" <broonie@...nel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "richard.leitner@...data.com" <richard.leitner@...data.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "f.fainelli@...il.com" <f.fainelli@...il.com>,
        "Quette, Arnaud" <ArnaudQuette@...on.com>
Subject: Re: [EXTERNAL]  Re: [PATCH net 0/4] Restore and fix PHY reset for
 SMSC LAN8720

> > > (ii) This defeats the purpose of a previous commit [2] that disabled
> > > the ref clock for power saving reasons. If a ref clock for the PHY is
> > > specified in DT, the SMSC driver will keep it always on (confirmed
> > > with scope).
> > 
> > NACK, the clock provider can be any clock. This has nothing to do with the
> > FEC clocks. The FEC _can_ be used as clock provider.
> 
> I'm sure you understand this much better than I do. What I can say is that I 
> directly measured the ref clk and found that when I add the clock to the DT
> the clock stays on forever. Basically it seems like the FEC calls to 
> clk_disable_unprepare() don't work in this case, though I'm not sure about the
> reason behind this.

The reason is easy to explain. The clock API is reference counted. It
counts how many times a clock is turned on and off. A clock has to be
turned off as many times as it was turned on before the hardware
actually turns off. So you have the FEC turning the clock on during
probe, followed by the phy turning the clock on. Some time later the
FEC turns the clock off for run time power saving, but there is still
one reference to the clock held by the PHY, so the hardware is left
ticking.

	Andrew