netdev - RE: [EXTERNAL] Re: [PATCH net 0/4] Restore and fix PHY reset for SMSC LAN8720

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Wed, 4 Nov 2020 13:14:06 +0000
From:   "Badel, Laurent" <LaurentBadel@...on.com>
To:     Andrew Lunn <andrew@...n.ch>
CC:     Marco Felsch <m.felsch@...gutronix.de>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "fugang.duan@....com" <fugang.duan@....com>,
        "kuba@...nel.org" <kuba@...nel.org>,
        Heiner Kallweit <hkallweit1@...il.com>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
        "lgirdwood@...il.com" <lgirdwood@...il.com>,
        "broonie@...nel.org" <broonie@...nel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "richard.leitner@...data.com" <richard.leitner@...data.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "f.fainelli@...il.com" <f.fainelli@...il.com>,
        "Quette, Arnaud" <ArnaudQuette@...on.com>
Subject: RE: [EXTERNAL]  Re: [PATCH net 0/4] Restore and fix PHY reset for
 SMSC LAN8720



> 

-----------------------------
Eaton Industries Manufacturing GmbH ~ Registered place of business: Route de la Longeraie 7, 1110, Morges, Switzerland 

-----------------------------

-----Original Message-----
> From: Andrew Lunn <andrew@...n.ch>
> Sent: Wednesday, November 04, 2020 2:11 PM
> To: Badel, Laurent <LaurentBadel@...on.com>
> Cc: Marco Felsch <m.felsch@...gutronix.de>; davem@...emloft.net;
> fugang.duan@....com; kuba@...nel.org; Heiner Kallweit
> <hkallweit1@...il.com>; linux@...linux.org.uk; p.zabel@...gutronix.de;
> lgirdwood@...il.com; broonie@...nel.org; robh+dt@...nel.org;
> richard.leitner@...data.com; netdev@...r.kernel.org;
> devicetree@...r.kernel.org; f.fainelli@...il.com; Quette, Arnaud
> <ArnaudQuette@...on.com>
> Subject: Re: [EXTERNAL] Re: [PATCH net 0/4] Restore and fix PHY reset for
> SMSC LAN8720
> 
> > > > (ii) This defeats the purpose of a previous commit [2] that
> > > > disabled the ref clock for power saving reasons. If a ref clock
> > > > for the PHY is specified in DT, the SMSC driver will keep it
> > > > always on (confirmed with scope).
> > >
> > > NACK, the clock provider can be any clock. This has nothing to do
> > > with the FEC clocks. The FEC _can_ be used as clock provider.
> >
> > I'm sure you understand this much better than I do. What I can say is
> > that I directly measured the ref clk and found that when I add the
> > clock to the DT the clock stays on forever. Basically it seems like
> > the FEC calls to
> > clk_disable_unprepare() don't work in this case, though I'm not sure
> > about the reason behind this.
> 
> The reason is easy to explain. The clock API is reference counted. It counts
> how many times a clock is turned on and off. A clock has to be turned off as
> many times as it was turned on before the hardware actually turns off. So
> you have the FEC turning the clock on during probe, followed by the phy
> turning the clock on. Some time later the FEC turns the clock off for run time
> power saving, but there is still one reference to the clock held by the PHY, so
> the hardware is left ticking.
> 
> 	Andrew

That makes a lot of sense, thanks very much for the explanation.