netdev - Re: [PATCH net] enetc: Workaround for MDIO register access issue

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Message-ID: <20201118180454.b3cxrkc4zqvwquln@skbuf>
Date:   Wed, 18 Nov 2020 20:04:54 +0200
From:   Vladimir Oltean <olteanv@...il.com>
To:     Jakub Kicinski <kuba@...nel.org>
Cc:     Andrew Lunn <andrew@...n.ch>,
        Claudiu Manoil <claudiu.manoil@....com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "David S . Miller" <davem@...emloft.net>,
        Alexandru Marginean <alexandru.marginean@....com>,
        Vladimir Oltean <vladimir.oltean@....com>
Subject: Re: [PATCH net] enetc: Workaround for MDIO register access issue

On Wed, Nov 18, 2020 at 09:03:43AM -0800, Jakub Kicinski wrote:
> On Wed, 18 Nov 2020 19:00:44 +0200 Vladimir Oltean wrote:
> > On Wed, Nov 18, 2020 at 02:38:56PM +0100, Andrew Lunn wrote:
> > > Thanks for the explanation. I don't think i've every reviewed a driver
> > > using read/write locks like this. But thinking it through, it does
> > > seem O.K.
> >
> > Thanks for reviewing and getting this merged. It sure is helpful to not
> > have the link flap while running iperf3 or other intensive network
> > activity.
> >
> > Even if this use of rwlocks may seem unconventional, I think it is the
> > right tool for working around the hardware bug.
>
> Out of curiosity - did you measure the performance hit?

It's not something that is noticeable, at least on 1Gbps where I'm
testing now. I'm not even sure what a valid metric would be. The CPU
utilization is about the same, the throughput across a 100 second iperf3
TCP test is the same (942 Mbits/sec at sender), and when I look at the
perf events for CPU cycles I get the feeling that any variation there is
mostly noise. There doesn't seem to be any outlier.

I might come back to this when I submit some hardware bug workarounds of
my own, for the 2.5Gbps ENETC that acts as a DSA master for the Ocelot
switch. There, I have a chance of testing at 2.5Gbps. But I don't have
that set up right now.