netdev - Re: [PATCH net-next v15 5/6] net: dsa: mv88e6xxx: Add support for mv88e6393x family of Marvell

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Message-ID: <20210112203808.4mkryi3tcut7mvz7@skbuf>
Date:   Tue, 12 Jan 2021 22:38:08 +0200
From:   Vladimir Oltean <olteanv@...il.com>
To:     Marek Behún <kabel@...nel.org>
Cc:     netdev@...r.kernel.org, pavana.sharma@...i.com,
        vivien.didelot@...il.com, f.fainelli@...il.com, kuba@...nel.org,
        lkp@...el.com, davem@...emloft.net, ashkan.boldaji@...i.com,
        andrew@...n.ch, Chris Packham <chris.packham@...iedtelesis.co.nz>,
        Russell King - ARM Linux admin <linux@...linux.org.uk>
Subject: Re: [PATCH net-next v15 5/6] net: dsa: mv88e6xxx: Add support for
 mv88e6393x family of Marvell

On Tue, Jan 12, 2021 at 08:54:04PM +0100, Marek Behún wrote:
> From: Pavana Sharma <pavana.sharma@...i.com>
> 
> The Marvell 88E6393X device is a single-chip integration of a 11-port
> Ethernet switch with eight integrated Gigabit Ethernet (GbE)
> transceivers and three 10-Gigabit interfaces.
> 
> This patch adds functionalities specific to mv88e6393x family (88E6393X,
> 88E6193X and 88E6191X).
> 
> The main differences between previous devices and this one are:
> - port 0 can be a SERDES port
> - all SERDESes are one-lane, eg. no XAUI nor RXAUI
> - on the other hand the SERDESes can do USXGMII, 10GBASER and 5GBASER
>   (on 6191X only one SERDES is capable of more than 1g; USXGMII is not
>   yet supported with this change)
> - Port Policy CTL register is changed to Port Policy MGMT CTL register,
>   via which several more registers can be accessed indirectly
> - egress monitor port is configured differently
> - ingress monitor/CPU/mirror ports are configured differently and can be
>   configured per port (ie. each port can have different ingress monitor
>   port, for example)
> - port speed AltBit works differently than previously
> - PHY registers can be also accessed via MDIO address 0x18 and 0x19
>   (on previous devices they could be accessed only via Global 2 offsets
>    0x18 and 0x19, which means two indirections; this feature is not yet
>    leveraged with this patch)
> 
> Co-developed-by: Ashkan Boldaji <ashkan.boldaji@...i.com>
> Signed-off-by: Ashkan Boldaji <ashkan.boldaji@...i.com>
> Signed-off-by: Pavana Sharma <pavana.sharma@...i.com>
> Co-developed-by: Marek Behún <kabel@...nel.org>
> Signed-off-by: Marek Behún <kabel@...nel.org>
> ---
>  drivers/net/dsa/mv88e6xxx/chip.c    | 149 +++++++++++++
>  drivers/net/dsa/mv88e6xxx/chip.h    |   4 +
>  drivers/net/dsa/mv88e6xxx/global1.h |   2 +
>  drivers/net/dsa/mv88e6xxx/global2.h |   8 +
>  drivers/net/dsa/mv88e6xxx/port.c    | 267 ++++++++++++++++++++++++
>  drivers/net/dsa/mv88e6xxx/port.h    |  47 ++++-
>  drivers/net/dsa/mv88e6xxx/serdes.c  | 312 ++++++++++++++++++++++++++++
>  drivers/net/dsa/mv88e6xxx/serdes.h  |  44 ++++
>  8 files changed, 831 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
> index ed07cb29b285..c2dc6858481a 100644
> --- a/drivers/net/dsa/mv88e6xxx/chip.c
> +++ b/drivers/net/dsa/mv88e6xxx/chip.c
> @@ -635,6 +635,28 @@ static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
>  	mv88e6390_phylink_validate(chip, port, mask, state);
>  }
>  
> +static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
> +					unsigned long *mask,
> +					struct phylink_link_state *state)
> +{
> +	if (port == 0 || port == 9 || port == 10) {
> +		phylink_set(mask, 10000baseT_Full);
> +		phylink_set(mask, 10000baseCR_Full);
> +		phylink_set(mask, 10000baseSR_Full);
> +		phylink_set(mask, 10000baseLR_Full);
> +		phylink_set(mask, 10000baseLRM_Full);
> +		phylink_set(mask, 10000baseER_Full);

Why did you remove 1000baseKR_Full from here?