netdev - Re: [PATCH net-next V2] net: dsa: microchip: Adjust reset release timing to match reference reset circuit

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Date:   Wed, 20 Jan 2021 10:14:40 +0000
From:   Paul Barker <pbarker@...sulko.com>
To:     Marek Vasut <marex@...x.de>
Cc:     Networking <netdev@...r.kernel.org>,
        Florian Fainelli <f.fainelli@...il.com>,
        Andrew Lunn <andrew@...n.ch>, Jakub Kicinski <kuba@...nel.org>,
        Michael Grzeschik <m.grzeschik@...gutronix.de>
Subject: Re: [PATCH net-next V2] net: dsa: microchip: Adjust reset release
 timing to match reference reset circuit

On Wed, 20 Jan 2021 at 03:05, Marek Vasut <marex@...x.de> wrote:
>
> KSZ8794CNX datasheet section 8.0 RESET CIRCUIT describes recommended
> circuit for interfacing with CPU/FPGA reset consisting of 10k pullup
> resistor and 10uF capacitor to ground. This circuit takes ~100 ms to
> rise enough to release the reset.
>
> For maximum supply voltage VDDIO=3.3V VIH=2.0V R=10kR C=10uF that is
>                     VDDIO - VIH
>   t = R * C * -ln( ------------- ) = 10000*0.00001*-(-0.93)=0.093 s
>                        VDDIO
> so we need ~95 ms for the reset to really de-assert, and then the
> original 100us for the switch itself to come out of reset. Simply
> msleep() for 100 ms which fits the constraint with a bit of extra
> space.

This makes sense if someone is using that device and following the
reference circuit exactly. Working with the ksz9477 I can tell you
that the reference reset circuit in figure 7.2 of the datasheet
doesn't work with a VDDIO of 1.8V. And hardware engineers like to take
some liberties anyway...

But 100ms is reasonable in general. It will allow for the expected
rise time of a wide range of possible reset circuit designs and isn't
so long that it will have a major impact on start-up time.

So it looks good to me.

Reviewed-by: Paul Barker <pbarker@...sulko.com>

-- 
Paul Barker
Konsulko Group