netdev - Re: [PATCH net-next V2] net: dsa: microchip: Adjust reset release timing to match reference reset circuit

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Date:   Wed, 20 Jan 2021 20:02:50 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Marek Vasut <marex@...x.de>
Cc:     netdev@...r.kernel.org, Florian Fainelli <f.fainelli@...il.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Michael Grzeschik <m.grzeschik@...gutronix.de>,
        Paul Barker <pbarker@...sulko.com>
Subject: Re: [PATCH net-next V2] net: dsa: microchip: Adjust reset release
 timing to match reference reset circuit

On Wed, Jan 20, 2021 at 04:05:02AM +0100, Marek Vasut wrote:
> KSZ8794CNX datasheet section 8.0 RESET CIRCUIT describes recommended
> circuit for interfacing with CPU/FPGA reset consisting of 10k pullup
> resistor and 10uF capacitor to ground. This circuit takes ~100 ms to
> rise enough to release the reset.
> 
> For maximum supply voltage VDDIO=3.3V VIH=2.0V R=10kR C=10uF that is
>                     VDDIO - VIH
>   t = R * C * -ln( ------------- ) = 10000*0.00001*-(-0.93)=0.093 s
>                        VDDIO
> so we need ~95 ms for the reset to really de-assert, and then the
> original 100us for the switch itself to come out of reset. Simply
> msleep() for 100 ms which fits the constraint with a bit of extra
> space.
> 
> Fixes: 5b797980908a ("net: dsa: microchip: Implement recommended reset timing")
> Reviewed-by: Florian Fainelli <f.fainelli@...il.com>
> Signed-off-by: Marek Vasut <marex@...x.de>
> Cc: Andrew Lunn <andrew@...n.ch>
> Cc: Florian Fainelli <f.fainelli@...il.com>
> Cc: Jakub Kicinski <kuba@...nel.org>
> Cc: Michael Grzeschik <m.grzeschik@...gutronix.de>
> Cc: Paul Barker <pbarker@...sulko.com>

Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew