netdev - RE: [pull request][net-next V10 00/14] Add mlx5 subfunction support

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Message-ID: <BY5PR12MB4322027CCDC2ECAF21174490DCBD9@BY5PR12MB4322.namprd12.prod.outlook.com>
Date:   Mon, 25 Jan 2021 20:26:57 +0000
From:   Parav Pandit <parav@...dia.com>
To:     Edwin Peer <edwin.peer@...adcom.com>,
        Jason Gunthorpe <jgg@...dia.com>
CC:     Saeed Mahameed <saeed@...nel.org>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        netdev <netdev@...r.kernel.org>,
        "linux-rdma@...r.kernel.org" <linux-rdma@...r.kernel.org>,
        Alexander Duyck <alexander.duyck@...il.com>,
        Sridhar Samudrala <sridhar.samudrala@...el.com>,
        David Ahern <dsahern@...nel.org>,
        Kiran Patil <kiran.patil@...el.com>,
        Jacob Keller <jacob.e.keller@...el.com>,
        "Ertman, David M" <david.m.ertman@...el.com>,
        "Dan Williams" <dan.j.williams@...el.com>,
        Saeed Mahameed <saeedm@...dia.com>
Subject: RE: [pull request][net-next V10 00/14] Add mlx5 subfunction support


> From: Edwin Peer <edwin.peer@...adcom.com>
> Sent: Tuesday, January 26, 2021 1:36 AM
> 
> On Mon, Jan 25, 2021 at 11:49 AM Jason Gunthorpe <jgg@...dia.com>
> wrote:
> 
> > I've never seen someone implement a NumVF > 256 by co-opting the bus
> > number.
> 
> Usually the VF offset already places the VF routing IDs into a
> different bus number range from the PF. That much at least works
> today.
> 
> > Can Linux even assign more bus numbers to a port without firmware
> > help? Bus numbers are something that requires the root complex to be
> > aware of to setup routability.
> 
> I'm not sure, presumably something already infers this for the first
> additional bus number based on the SR-IOV config capability?
> 
It is not inferred.
Linux pci core programs the additional registers for subordinate and secondary bus numbers.
Though, it comes with its own extra hw cost.

Keep in mind how 1000 Vfs are enabled and disabled in one go at pci spec level and so at OS level, as opposed to unit of one here.
PCI comes with heavy bus level reset requirement apart from AER and more.