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Date:   Tue, 26 Jan 2021 00:39:20 +0000
From:   "Saleem, Shiraz" <shiraz.saleem@...el.com>
To:     Leon Romanovsky <leon@...nel.org>
CC:     "dledford@...hat.com" <dledford@...hat.com>,
        "jgg@...dia.com" <jgg@...dia.com>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "linux-rdma@...r.kernel.org" <linux-rdma@...r.kernel.org>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "Ertman, David M" <david.m.ertman@...el.com>,
        "Nguyen, Anthony L" <anthony.l.nguyen@...el.com>,
        "Ismail, Mustafa" <mustafa.ismail@...el.com>
Subject: RE: [PATCH 07/22] RDMA/irdma: Register an auxiliary driver and
 implement private channel OPs

> Subject: Re: [PATCH 07/22] RDMA/irdma: Register an auxiliary driver and
> implement private channel OPs
> 
> 
> > +static int irdma_devlink_rsrc_limits_validate(struct devlink *dl, u32 id,
> > +					      union devlink_param_value val,
> > +					      struct netlink_ext_ack *extack) {
> > +	u8 value = val.vu8;
> > +
> > +	if (value > 7) {
> > +		NL_SET_ERR_MSG_MOD(extack, "resource limits selector range
> is (0-7)");
> > +		return -ERANGE;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int irdma_devlink_enable_roce_validate(struct devlink *dl, u32 id,
> > +					      union devlink_param_value val,
> > +					      struct netlink_ext_ack *extack) {
> > +	struct irdma_dl_priv *priv = devlink_priv(dl);
> > +	bool value = val.vbool;
> > +
> > +	if (value && priv->drvdata->hw_ver == IRDMA_GEN_1) {
> > +		NL_SET_ERR_MSG_MOD(extack, "RoCE not supported on
> device");
> > +		return -EOPNOTSUPP;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static int irdma_devlink_upload_ctx_get(struct devlink *devlink, u32 id,
> > +					struct devlink_param_gset_ctx *ctx) {
> > +	ctx->val.vbool = irdma_upload_context;
> > +	return 0;
> > +}
> > +
> > +static int irdma_devlink_upload_ctx_set(struct devlink *devlink, u32 id,
> > +					struct devlink_param_gset_ctx *ctx) {
> > +	irdma_upload_context = ctx->val.vbool;
> > +	return 0;
> > +}
> > +
> > +enum irdma_dl_param_id {
> > +	IRDMA_DEVLINK_PARAM_ID_BASE =
> DEVLINK_PARAM_GENERIC_ID_MAX,
> > +	IRDMA_DEVLINK_PARAM_ID_LIMITS_SELECTOR,
> > +	IRDMA_DEVLINK_PARAM_ID_UPLOAD_CONTEXT,
> > +};
> > +
> > +static const struct devlink_param irdma_devlink_params[] = {
> > +
> 	DEVLINK_PARAM_DRIVER(IRDMA_DEVLINK_PARAM_ID_LIMITS_SELE
> CTOR,
> > +			     "resource_limits_selector",
> DEVLINK_PARAM_TYPE_U8,
> > +			      BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
> > +			      NULL, NULL, irdma_devlink_rsrc_limits_validate),
> > +
> 	DEVLINK_PARAM_DRIVER(IRDMA_DEVLINK_PARAM_ID_UPLOAD_CON
> TEXT,
> > +			     "upload_context", DEVLINK_PARAM_TYPE_BOOL,
> > +			     BIT(DEVLINK_PARAM_CMODE_RUNTIME),
> > +			     irdma_devlink_upload_ctx_get,
> > +			     irdma_devlink_upload_ctx_set, NULL),
> > +	DEVLINK_PARAM_GENERIC(ENABLE_ROCE,
> BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
> > +			      NULL, NULL, irdma_devlink_enable_roce_validate),
> > +};
> 
> RoCE enable knob is understandable, but others are not explained.
> 

OK. That can be fixed.

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