Date:   Tue, 2 Feb 2021 02:53:06 +0200
From:   Vladimir Oltean <olteanv@...il.com>
To:     Florian Fainelli <f.fainelli@...il.com>
Cc:     netdev <netdev@...r.kernel.org>
Subject: Re: About PHY_INTERFACE_MODE_REVMII

Hi Florian,

Thanks for the quick answer!

On Mon, Feb 01, 2021 at 04:26:36PM -0800, Florian Fainelli wrote:
> It depends on the level of control that you have and expect more on that
> below.

> That is true if we consider that you can use an electrical connection
> other than MII, which was the flaw in the reasoning leading to introduce
> the above commit. If you took the name reverse MII literally like I did,
> you would not think it would apply to anything but MII and maybe reduced
> MII, but not GMII or RGMII. More on that below.

> I don't believe I ever saw a system that used reverse MII and yet did
> not use either plain MII as far as the electrical connections went. That
> does not mean you could not electrically connect these two systems using
> RMII, GMII or something else. With RGMII, I don't see the point in using
> a RevMII block especially as far as clocking goes, both link partners
> can have their own local clock and just do clock recovery upon receive.
>
> When this commit was done, the only use case that had to be supported
> was the case of two Ethernet MACs (one a video decoder, the other a
> cable modem) connected over a MII electrical connection and we could not
> change the cable modem side, so we act to make ourselves "look like" a
> PHY which the hardware supported. Back then the GENET driver was just
> getting a facelift to use PHYLIB and so it still used a fixed-link plus
> phy-mode = "rev-mii" to get that mode to work which was probably too big
> of a shortcut in addition to the flaw in the reasoning about what RevMII
> really was.
>
> If you would like to deprecate/warn when using PHY_INTERFACE_MODE_REVMII
> value and come up with a better way to represent such links, no issues
> with me, it looks like we have a few in tree users to convert.

Well, everything depends on whether a formal specification of RevMII
exists or not. If you're sure that all users of PHY_INTERFACE_MODE_REVMII
actually use the 8-bit wide parallel data interface that runs at 25 MHz
and 100 Mbps ("that" MII), just that they operate in MII PHY mode instead
of MII MAC, then I can work with that, no reason to deprecate it.

The problem is that I saw no online reference of RevMII + RMII = RevRMII,
which would make just as much sense as RevMII. And as I said, RGMII does
support in-band signaling, it's just probably too obscure to see it in
the wild or rely on it. RGMII without in-band signaling has no reason to
differentiate between MAC and PHY role, but taking the inband signaling
into account it does. So RevRGMII might be a thing too.

For example, the sja1105 supports MII MAC, MII PHY, RMII MAC, RMII PHY
modes. But it doesn't export a clause 22 virtual PHY register map to
neither end of the link - it doesn't have any MDIO connection at all.
Does the sja1105 support RevMII or does it not? If RevMII means MII PHY
and the clause 22 interface is just optional (like it is for normal MII,
RMII, RGMII which can operate in fixed-link too), then I'd say yes,
sja1105 supports RevMII. But if RevMII is _defined_ by that standardized
clause 22 interface, then no it doesn't.

In the DSA driver, I created some custom device tree bindings to solve
the situation where you'd have two sja1105 devices connected MAC to MAC
using RMII or MII: sja1105,role-mac and sja1105,role-phy. There are no
in-tree users of these DT properties, so depending on how this
conversation goes, I might just go ahead and do the other thing: say
that RevRMII exists and the clause 22 PHY registers are optional, add
PHY_INTERFACE_MODE_REVRMII, and declare that sja1105 supports
PHY_INTERFACE_MODE_REVMII which is the equivalent of what is currently
done with PHY_INTERFACE_MODE_MII + sja1105,role-phy, and
PHY_INTERFACE_MODE_REVRMII.

Having a separate PHY interface mode for RevRMII would solve the situation
where you have two instances of the same driver at the two ends of the
same link, seeing the same PHY registers, but nonetheless needing to
configure themselves in different modes and not having what to base that
decision on. What do you think?

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