netdev - Re: [PATCH bpf-next] bpf: arm64: Redefine MOV consistent with arch insn

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Message-ID: <20210330093149.GA5281@willie-the-truck>
Date:   Tue, 30 Mar 2021 10:31:49 +0100
From:   Will Deacon <will@...nel.org>
To:     Jianlin Lv <Jianlin.Lv@....com>
Cc:     bpf@...r.kernel.org, zlim.lnx@...il.com, catalin.marinas@....com,
        ast@...nel.org, daniel@...earbox.net, andrii@...nel.org,
        kafai@...com, songliubraving@...com, yhs@...com,
        john.fastabend@...il.com, kpsingh@...nel.org,
        linux-kernel@...r.kernel.org, netdev@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, iecedge@...il.com
Subject: Re: [PATCH bpf-next] bpf: arm64: Redefine MOV consistent with arch
 insn

On Tue, Mar 30, 2021 at 03:42:35PM +0800, Jianlin Lv wrote:
> A64_MOV is currently mapped to Add Instruction. Architecturally MOV
> (register) is an alias of ORR (shifted register) and MOV (to or from SP)
> is an alias of ADD (immediate).
> This patch redefines A64_MOV and uses existing functionality
> aarch64_insn_gen_move_reg() in insn.c to encode MOV (register) instruction.
> For moving between register and stack pointer, rename macro to A64_MOV_SP.

What does this gain us? There's no requirement for a BPF "MOV" to match an
arm64 architectural "MOV", so what's the up-side of aligning them like this?

Cheers,

Will