netdev - Re: [PATCH bpf-next] bpf: arm64: Redefine MOV consistent with arch insn

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Message-ID: <CAFA-uR8_N=RHbhm4PdiB-AMCBdXsoMyM-9WgaPxPQ7-ZF6ujXA@mail.gmail.com>
Date:   Wed, 31 Mar 2021 17:22:18 +0800
From:   Jianlin Lv <iecedge@...il.com>
To:     Will Deacon <will@...nel.org>
Cc:     Jianlin Lv <Jianlin.Lv@....com>, bpf <bpf@...r.kernel.org>,
        zlim.lnx@...il.com, catalin.marinas@....com,
        Alexei Starovoitov <ast@...nel.org>,
        Daniel Borkmann <daniel@...earbox.net>,
        Andrii Nakryiko <andrii@...nel.org>,
        Martin KaFai Lau <kafai@...com>,
        Song Liu <songliubraving@...com>, Yonghong Song <yhs@...com>,
        John Fastabend <john.fastabend@...il.com>,
        KP Singh <kpsingh@...nel.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Network Development <netdev@...r.kernel.org>,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH bpf-next] bpf: arm64: Redefine MOV consistent with arch insn

On Tue, Mar 30, 2021 at 5:31 PM Will Deacon <will@...nel.org> wrote:
>
> On Tue, Mar 30, 2021 at 03:42:35PM +0800, Jianlin Lv wrote:
> > A64_MOV is currently mapped to Add Instruction. Architecturally MOV
> > (register) is an alias of ORR (shifted register) and MOV (to or from SP)
> > is an alias of ADD (immediate).
> > This patch redefines A64_MOV and uses existing functionality
> > aarch64_insn_gen_move_reg() in insn.c to encode MOV (register) instruction.
> > For moving between register and stack pointer, rename macro to A64_MOV_SP.
>
> What does this gain us? There's no requirement for a BPF "MOV" to match an
> arm64 architectural "MOV", so what's the up-side of aligning them like this?
>
> Cheers,
>
> Will

According to the description in the Arm Software Optimization Guide,
Arithmetic(basic) and Logical(basic) instructions have the same
Exec Latency and Execution Throughput.
This change did not bring about a performance improvement.
The original intention was to make the instruction map more 'natively'.

Jianlin