netdev - Re: Realtek 8139 problem on 486.

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Message-ID: <alpine.DEB.2.21.2106211623090.779@angie.orcam.me.uk>
Date:   Mon, 21 Jun 2021 16:42:19 +0200 (CEST)
From:   "Maciej W. Rozycki" <macro@...am.me.uk>
To:     Arnd Bergmann <arnd@...nel.org>
cc:     Thomas Gleixner <tglx@...utronix.de>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Nikolai Zhubr <zhubr.2@...il.com>,
        netdev <netdev@...r.kernel.org>, Jeff Garzik <jgarzik@...ox.com>,
        the arch/x86 maintainers <x86@...nel.org>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        "H. Peter Anvin" <hpa@...or.com>
Subject: Re: Realtek 8139 problem on 486.

On Mon, 21 Jun 2021, Arnd Bergmann wrote:

> >  A warning surely won't hurt, but TBH I'd just reprogram any incorrectly
> > configured PCI interrupt line unconditionally where the ELCR is available.
> > The chance someone uses a broken PCI card that drives its interrupt line
> > as edge-triggered and is actually handled by a Linux driver both at a time
> > is IMO nil.  Such a card requires special provisions hardly any system
> > provides and has anyone here seen a report of such a beast?
> 
> I looked some more through the git history and found at least one time
> that the per-chipset ELCR fixup came up for discussion[1], and this
> appears to have resulted in generalizing an ALI specific fixup into
> common code into common code[2], so we should already be doing
> exactly this in many cases. If Nikolai can boot the system with debugging
> enabled for arch/x86/pci/irq.c, we should be able to see exactly
> which code path is his in his case, and why it doesn't go through
> setting that register at the moment.
> 
> I also found an slightly more recent discussion, from where it seems
> that the authoritative decision when it came up in the past was that edge
> triggered interrupts are supposed to work as long as they are not
> shared [3][4].

 Sadly Linus's rule applies both ways: if a device has been designed with 
level-triggered interrupts in mind, there may be no race-free way to 
ensure an active-to-inactive-to-active transition has happened on its IRQ 
line as the driver acknowledges handling in the relevant device's CSR.  

 The rule of thumb is to acknowledge early in the handler, and to work 
around broken configurations it may be desirable to also briefly mask all 
the interrupt sources with the device so as to make sure it deasserts its 
IRQ line even if another interrupt has already been queued.  OTOH if IRQ
sharing is to be supported a device absolutely has to have an interrupt 
mask register, as the system cannot rely on masking at the interrupt 
controller if multiple devices are to be handled with a single line.  I 
suspect many of our drivers do not do such precautionary masking though.

 Is there a mask register with the 8139?

 NB I find it amazing how people can break such relatively simple 
concepts, like not getting PCI IRQ steering right in early designs or 
messing up edge and level triggering.  I mean wired interrupts are not 
rocket science.  Sigh...

  Maciej