netdev - Re: [PATCH net-next 1/3] arm64: barrier: add DGH macros to control memory accesses merging

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Message-ID: <20210622123221.GA71782@C02TD0UTHF1T.local>
Date:   Tue, 22 Jun 2021 13:32:21 +0100
From:   Mark Rutland <mark.rutland@....com>
To:     Will Deacon <will@...nel.org>
Cc:     Guangbin Huang <huangguangbin2@...wei.com>, davem@...emloft.net,
        kuba@...nel.org, catalin.marinas@....com, maz@...nel.org,
        dbrazdil@...gle.com, qperret@...gle.com, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        lipeng321@...wei.com, peterz@...radead.org
Subject: Re: [PATCH net-next 1/3] arm64: barrier: add DGH macros to control
 memory accesses merging

On Tue, Jun 22, 2021 at 01:16:31PM +0100, Will Deacon wrote:
> On Tue, Jun 22, 2021 at 07:11:09PM +0800, Guangbin Huang wrote:
> > From: Xiongfeng Wang <wangxiongfeng2@...wei.com>
> > 
> > DGH prohibits merging memory accesses with Normal-NC or Device-GRE
> > attributes before the hint instruction with any memory accesses
> > appearing after the hint instruction. Provide macros to expose it to the
> > arch code.
> 
> Hmm.
> 
> The architecture states:
> 
>   | DGH is a hint instruction. A DGH instruction is not expected to be
>   | performance optimal to merge memory accesses with Normal Non-cacheable
>   | or Device-GRE attributes appearing in program order before the hint
>   | instruction with any memory accesses appearing after the hint instruction
>   | into a single memory transaction on an interconnect.
> 
> which doesn't make a whole lot of sense to me, in all honesty.

I think there are some missing words, and this was supposed to say
something like:

| DGH is a hint instruction. A DGH instruction *indicates that it* is
| not expected to be performance optimal to merge memory accesses with
| Normal Non-cacheable or Device-GRE attributes appearing in program
| order before the hint instruction with any memory accesses appearing
| after the hint instruction into a single memory transaction on an
| interconnect.

... i.e. it's a hint to the CPU to avoid merging accesses which are
either side of the DGH, so that the prior accesses don't get
indefinitely delayed waiting to be merged.

I'll try to get the documentation fixed, since as-is the wording does
not make sense.

Thanks,
Mark.