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Date: Mon, 2 Aug 2021 17:00:46 +0300 From: Vladimir Oltean <olteanv@...il.com> To: Oleksij Rempel <o.rempel@...gutronix.de> Cc: Andrew Lunn <andrew@...n.ch>, Vivien Didelot <vivien.didelot@...il.com>, Florian Fainelli <f.fainelli@...il.com>, "David S. Miller" <davem@...emloft.net>, Jakub Kicinski <kuba@...nel.org>, Russell King <linux@...linux.org.uk>, Pengutronix Kernel Team <kernel@...gutronix.de>, netdev@...r.kernel.org, linux-kernel@...r.kernel.org, linux-mips@...r.kernel.org Subject: Re: [PATCH net-next v3 1/6] net: dsa: qca: ar9331: reorder MDIO write sequence On Mon, Aug 02, 2021 at 03:10:32PM +0200, Oleksij Rempel wrote: > In case of this switch we work with 32bit registers on top of 16bit > bus. Some registers (for example access to forwarding database) have > trigger bit on the first 16bit half of request and the result + > configuration of request in the second half. Without this patch, we would > trigger database operation and overwrite result in one run. > > To make it work properly, we should do the second part of transfer > before the first one is done. > > So far, this rule seems to work for all registers on this switch. > > Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de> > Reviewed-by: Andrew Lunn <andrew@...n.ch> > --- Reviewed-by: Vladimir Oltean <olteanv@...il.com>
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