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Message-Id: <20220112181113.875567-4-robert.hancock@calian.com>
Date: Wed, 12 Jan 2022 12:11:13 -0600
From: Robert Hancock <robert.hancock@...ian.com>
To: netdev@...r.kernel.org
Cc: davem@...emloft.net, kuba@...nel.org, robh+dt@...nel.org,
michal.simek@...inx.com, nicolas.ferre@...rochip.com,
claudiu.beznea@...rochip.com, devicetree@...r.kernel.org,
Robert Hancock <robert.hancock@...ian.com>
Subject: [PATCH net-next 3/3] arm64: dts: zynqmp: Added GEM reset definitions
The Cadence GEM/MACB driver now utilizes the platform-level reset on the
ZynqMP platform. Add reset definitions to the ZynqMP platform device
tree to allow this to be used.
Signed-off-by: Robert Hancock <robert.hancock@...ian.com>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 74e66443e4ce..9bec3ba20c69 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -512,6 +512,8 @@ gem0: ethernet@...b0000 {
#stream-id-cells = <1>;
iommus = <&smmu 0x874>;
power-domains = <&zynqmp_firmware PD_ETH_0>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
+ reset-names = "gem0_rst";
};
gem1: ethernet@...c0000 {
@@ -526,6 +528,8 @@ gem1: ethernet@...c0000 {
#stream-id-cells = <1>;
iommus = <&smmu 0x875>;
power-domains = <&zynqmp_firmware PD_ETH_1>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
+ reset-names = "gem1_rst";
};
gem2: ethernet@...d0000 {
@@ -540,6 +544,8 @@ gem2: ethernet@...d0000 {
#stream-id-cells = <1>;
iommus = <&smmu 0x876>;
power-domains = <&zynqmp_firmware PD_ETH_2>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
+ reset-names = "gem2_rst";
};
gem3: ethernet@...e0000 {
@@ -554,6 +560,8 @@ gem3: ethernet@...e0000 {
#stream-id-cells = <1>;
iommus = <&smmu 0x877>;
power-domains = <&zynqmp_firmware PD_ETH_3>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;
+ reset-names = "gem3_rst";
};
gpio: gpio@...a0000 {
--
2.31.1
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