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Date: Thu, 13 Jan 2022 16:27:11 +0000 From: Robert Hancock <robert.hancock@...ian.com> To: "radheys@...inx.com" <radheys@...inx.com>, "netdev@...r.kernel.org" <netdev@...r.kernel.org> CC: "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>, "davem@...emloft.net" <davem@...emloft.net>, "kuba@...nel.org" <kuba@...nel.org>, "daniel@...earbox.net" <daniel@...earbox.net>, "michals@...inx.com" <michals@...inx.com>, "ariane.keller@....ee.ethz.ch" <ariane.keller@....ee.ethz.ch>, "harinik@...inx.com" <harinik@...inx.com> Subject: Re: [PATCH net v2 2/9] net: axienet: Wait for PhyRstCmplt after core reset On Thu, 2022-01-13 at 11:53 +0000, Radhey Shyam Pandey wrote: > > -----Original Message----- > > From: Robert Hancock <robert.hancock@...ian.com> > > Sent: Wednesday, January 12, 2022 11:07 PM > > To: netdev@...r.kernel.org > > Cc: Radhey Shyam Pandey <radheys@...inx.com>; davem@...emloft.net; > > kuba@...nel.org; linux-arm-kernel@...ts.infradead.org; Michal Simek > > <michals@...inx.com>; ariane.keller@....ee.ethz.ch; daniel@...earbox.net; > > Robert Hancock <robert.hancock@...ian.com> > > Subject: [PATCH net v2 2/9] net: axienet: Wait for PhyRstCmplt after core > > reset > > > > When resetting the device, wait for the PhyRstCmplt bit to be set > > in the interrupt status register before continuing initialization, to > > ensure that the core is actually ready. The MgtRdy bit could also be > > waited for, but unfortunately when using 7-series devices, the bit does > > Just to understand - can you share 7- series design details. > Based on documentation - This MgtRdy bit indicates if the TEMAC core is > out of reset and ready for use. In systems that use an serial transceiver, > this bit goes to 1 when the serial transceiver is ready to use. From what I saw, the bit behaved as described on ZynqMP where it would go to 1 during initialization, but on a Kintex-7 design with this core, the bit never seemed to go to 1 until an actual link was established on the transceiver, so it wasn't really usable in this situation. > > Also if we don't wait for phy reset - what is the issue we are seeing? This is more for the case of using an external PHY device - we shouldn't be proceeding to MDIO initialization and potentially trying to talk to the PHY when it is potentially still in reset.. > > > not appear to work as documented (it seems to behave as some sort of > > link state indication and not just an indication the transceiver is > > ready) so it can't really be relied on. > > > > Fixes: 8a3b7a252dca9 ("drivers/net/ethernet/xilinx: added Xilinx AXI > > Ethernet > > driver") > > Signed-off-by: Robert Hancock <robert.hancock@...ian.com> > > --- > > drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > > b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > > index f950342f6467..f425a8404a9b 100644 > > --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > > +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > > @@ -516,6 +516,16 @@ static int __axienet_device_reset(struct axienet_local > > *lp) > > return ret; > > } > > > > + /* Wait for PhyRstCmplt bit to be set, indicating the PHY reset has > > finished */ > > + ret = read_poll_timeout(axienet_ior, value, > > + value & XAE_INT_PHYRSTCMPLT_MASK, > > + DELAY_OF_ONE_MILLISEC, 50000, false, lp, > > + XAE_IS_OFFSET); > > + if (ret) { > > + dev_err(lp->dev, "%s: timeout waiting for PhyRstCmplt\n", > > __func__); > > + return ret; > > + } > > + > > return 0; > > } > > > > -- > > 2.31.1 -- Robert Hancock Senior Hardware Designer, Calian Advanced Technologies www.calian.com
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