netdev - Re: [PATCH net v2 0/9] Xilinx axienet fixes

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Message-ID: <5a5b1c7d58b81b2a6ab738650964ea7a1c2cf99b.camel@calian.com>
Date:   Tue, 18 Jan 2022 20:45:31 +0000
From:   Robert Hancock <robert.hancock@...ian.com>
To:     "netdev@...r.kernel.org" <netdev@...r.kernel.org>
CC:     "andrew@...n.ch" <andrew@...n.ch>,
        "daniel@...earbox.net" <daniel@...earbox.net>,
        "radhey.shyam.pandey@...inx.com" <radhey.shyam.pandey@...inx.com>,
        "michal.simek@...inx.com" <michal.simek@...inx.com>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "ariane.keller@....ee.ethz.ch" <ariane.keller@....ee.ethz.ch>
Subject: Re: [PATCH net v2 0/9] Xilinx axienet fixes

On Wed, 2022-01-12 at 11:36 -0600, Robert Hancock wrote:
> Various fixes for the Xilinx AXI Ethernet driver.
> 
> Changed since v1:
> -corrected a Fixes tag to point to mainline commit
> -split up reset changes into 3 patches
> -added ratelimit on netdev_warn in TX busy case
> 
> Robert Hancock (9):
>   net: axienet: increase reset timeout
>   net: axienet: Wait for PhyRstCmplt after core reset
>   net: axienet: reset core on initialization prior to MDIO access
>   net: axienet: add missing memory barriers
>   net: axienet: limit minimum TX ring size
>   net: axienet: Fix TX ring slot available check
>   net: axienet: fix number of TX ring slots for available check
>   net: axienet: fix for TX busy handling
>   net: axienet: increase default TX ring size to 128
> 
>  .../net/ethernet/xilinx/xilinx_axienet_main.c | 135 +++++++++++-------
>  1 file changed, 84 insertions(+), 51 deletions(-)
> 

Hi all,

Any other comments/reviews on this patch set? It's marked as Changes Requested
in Patchwork, but I don't think I saw any discussions that ended up with any
changes being asked for?

-- 
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com