netdev - Re: [PATCH net-next 2/3] net: macb: Added ZynqMP-specific initialization

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Date:   Thu, 13 Jan 2022 08:27:50 +0100
From:   Michal Simek <michal.simek@...inx.com>
To:     Robert Hancock <robert.hancock@...ian.com>,
        <netdev@...r.kernel.org>, Harini Katakam <harinik@...inx.com>,
        Piyush Mehta <piyush.mehta@...inx.com>
CC:     <davem@...emloft.net>, <kuba@...nel.org>, <robh+dt@...nel.org>,
        <michal.simek@...inx.com>, <nicolas.ferre@...rochip.com>,
        <claudiu.beznea@...rochip.com>, <devicetree@...r.kernel.org>
Subject: Re: [PATCH net-next 2/3] net: macb: Added ZynqMP-specific
 initialization



On 1/12/22 19:11, Robert Hancock wrote:
> The GEM controllers on ZynqMP were missing some initialization steps which
> are required in some cases when using SGMII mode, which uses the PS-GTR
> transceivers managed by the phy-zynqmp driver.
> 
> The GEM core appears to need a hardware-level reset in order to work
> properly in SGMII mode in cases where the GT reference clock was not
> present at initial power-on. This can be done using a reset mapped to
> the zynqmp-reset driver in the device tree.
> 
> Also, when in SGMII mode, the GEM driver needs to ensure the PHY is
> initialized and powered on when it is initializing.
> 
> Signed-off-by: Robert Hancock <robert.hancock@...ian.com>
> ---
>   drivers/net/ethernet/cadence/macb_main.c | 47 +++++++++++++++++++++++-
>   1 file changed, 46 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
> index a363da928e8b..65b0360c487a 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -34,7 +34,9 @@
>   #include <linux/udp.h>
>   #include <linux/tcp.h>
>   #include <linux/iopoll.h>
> +#include <linux/phy/phy.h>
>   #include <linux/pm_runtime.h>
> +#include <linux/reset.h>
>   #include "macb.h"
>   
>   /* This structure is only used for MACB on SiFive FU540 devices */
> @@ -4455,6 +4457,49 @@ static int fu540_c000_init(struct platform_device *pdev)
>   	return macb_init(pdev);
>   }
>   
> +static int zynqmp_init(struct platform_device *pdev)
> +{
> +	struct net_device *dev = platform_get_drvdata(pdev);
> +	struct macb *bp = netdev_priv(dev);
> +	int ret;
> +
> +	/* Fully reset GEM controller at hardware level using zynqmp-reset driver,
> +	 * if mapped in device tree.
> +	 */
> +	ret = device_reset(&pdev->dev);
> +	if (ret) {
> +		dev_err_probe(&pdev->dev, ret, "failed to reset controller");
> +		return ret;
> +	}
> +
> +	if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
> +		/* Ensure PS-GTR PHY device used in SGMII mode is ready */
> +		struct phy *sgmii_phy = devm_phy_get(&pdev->dev, "sgmii-phy");
> +
> +		if (IS_ERR(sgmii_phy)) {
> +			ret = PTR_ERR(sgmii_phy);
> +			dev_err_probe(&pdev->dev, ret,
> +				      "failed to get PS-GTR PHY\n");
> +			return ret;
> +		}
> +
> +		ret = phy_init(sgmii_phy);
> +		if (ret) {
> +			dev_err(&pdev->dev, "failed to init PS-GTR PHY: %d\n",
> +				ret);
> +			return ret;
> +		}

I was playing with it recently on u-boot side and device reset should happen 
between phy init and phy power on to finish calibration.
At least that's I was told and that's I use in u-boot driver.

Harini/Piyush: Please correct me if I am wrong.

Thanks,
Michal