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Message-ID: <YgJre2C9jpfMCXSZ@lunn.ch>
Date: Tue, 8 Feb 2022 14:09:15 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Prasanna Vengateshan <prasanna.vengateshan@...rochip.com>
Cc: netdev@...r.kernel.org, olteanv@...il.com, robh+dt@...nel.org,
UNGLinuxDriver@...rochip.com, woojung.huh@...rochip.com,
hkallweit1@...il.com, linux@...linux.org.uk, davem@...emloft.net,
kuba@...nel.org, linux-kernel@...r.kernel.org,
vivien.didelot@...il.com, f.fainelli@...il.com,
devicetree@...r.kernel.org
Subject: Re: [PATCH v8 net-next 03/10] net: phy: Add support for LAN937x T1
phy driver
On Mon, Feb 07, 2022 at 10:51:57PM +0530, Prasanna Vengateshan wrote:
> Added support for Microchip LAN937x T1 phy driver. The sequence of
> initialization is used commonly for both LAN87xx and LAN937x
> drivers. The new initialization sequence is an improvement to
> existing LAN87xx and it is shared with LAN937x.
>
> Also relevant comments are added in the existing code and existing
> soft-reset customized code has been replaced with
> genphy_soft_reset().
>
> access_ereg_clr_poll_timeout() API is introduced for polling phy
> bank write and this is linked with PHYACC_ATTR_MODE_POLL.
>
> Finally introduced function table for LAN937X_T1_PHY_ID along with
> microchip_t1_phy_driver struct.
Hi Prasanna
That is a lot of changes in one patch.
I would suggest you make this a patch series of its own. It should be
independent of the switch changes. And then you can break this patch
up into a number of smaller patches.
Thanks
Andrew
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