netdev - Re: [PATCH] net: axiemac: initialize PHY before device reset

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 18 Mar 2022 01:37:08 +0800
From:   Andy Chiu <andy.chiu@...ive.com>
To:     Robert Hancock <robert.hancock@...ian.com>
Cc:     "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "michal.simek@...inx.com" <michal.simek@...inx.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "greentime.hu@...ive.com" <greentime.hu@...ive.com>,
        radhey.shyam.pandey@...inx.com
Subject: Re: [PATCH] net: axiemac: initialize PHY before device reset

Thanks for pointing that out.

Though it is weird, it should be safe to do that. The reset of the
MDIO interface would not affect any r/w through the bus afterwards
since the driver would re-initialize the MDIO interface whenever it
uses `mdiobus_write()` or `mdiobus_read()` for bus transactions.
However, some of the very first packet on the rx side might get
processed incompletely since `phylink_of_phy_connect()` will
eventually call `phy_resume()`, which brings the phy active earlier
than the reset of the core.

The reason why we have this change in ordering is that the clock of
our PCS/PMA PHY is sourced from the SGMII ref clock of the external
PHY, which is not enabled by default. The only way to get the PCS/PMA
PHY stable here is to start the clock (initialize the external PHY)
before the reset takes place. We have limited clock sources on the
vcu118 FPGA board, and this happens to be our way to configure it. I
think it is a hack on both sw and hw, but still wonder if anyone under
such hw configuration, if exist, would like to have the patch.

               |<---ref clock-----|
+----------+---^---+         +------+
| Xilinx's |  PCS/ |         | Ti's |
| Ethernet |  PMA  |--SGMII--| PHY  |
|          |  PHY  |         |      |
+----------+-------+         +------+
      |--------|--- MDIO---------|

loop-in: radhey.shyam.pandey@...inx.com

Andy

Andy