netdev - Re: [PATCH 0/2] Add reset deassertion for Aspeed MDIO

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <YjhrUrXzLxvKtDP8@lunn.ch>
Date:   Mon, 21 Mar 2022 13:10:58 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Dylan Hung <dylan_hung@...eedtech.com>
Cc:     robh+dt@...nel.org, joel@....id.au, andrew@...id.au,
        hkallweit1@...il.com, linux@...linux.org.uk, davem@...emloft.net,
        kuba@...nel.org, pabeni@...hat.com, p.zabel@...gutronix.de,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-aspeed@...ts.ozlabs.org, linux-kernel@...r.kernel.org,
        netdev@...r.kernel.org, BMC-SW@...eedtech.com
Subject: Re: [PATCH 0/2] Add reset deassertion for Aspeed MDIO

On Mon, Mar 21, 2022 at 03:01:29PM +0800, Dylan Hung wrote:
> Add missing reset deassertion for Aspeed MDIO. There are 4 MDIOs
> embedded in Aspeed AST2600 and share one reset control bit SCU50[3].

Is the reset limited to the MDIO bus masters, or are PHYs one the bus
potentially also reset?

Who asserts the reset in the first place? Don't you want the first
MDIO bus to probe to assert and then deassert the reset in order that
all the hardware is reset?

    Andrew