netdev - RE: [PATCH 0/2] Add reset deassertion for Aspeed MDIO

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Message-ID: <HK0PR06MB283430933D2FE015531B52749C179@HK0PR06MB2834.apcprd06.prod.outlook.com>
Date:   Tue, 22 Mar 2022 09:10:28 +0000
From:   Dylan Hung <dylan_hung@...eedtech.com>
To:     Andrew Lunn <andrew@...n.ch>
CC:     "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "joel@....id.au" <joel@....id.au>,
        "andrew@...id.au" <andrew@...id.au>,
        "hkallweit1@...il.com" <hkallweit1@...il.com>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "pabeni@...hat.com" <pabeni@...hat.com>,
        "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-aspeed@...ts.ozlabs.org" <linux-aspeed@...ts.ozlabs.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        BMC-SW <BMC-SW@...eedtech.com>
Subject: RE: [PATCH 0/2] Add reset deassertion for Aspeed MDIO

Hi Andrew,

> -----Original Message-----
> From: Andrew Lunn [mailto:andrew@...n.ch]
> Sent: 2022年3月21日 8:11 PM
> To: Dylan Hung <dylan_hung@...eedtech.com>
> Cc: robh+dt@...nel.org; joel@....id.au; andrew@...id.au;
> hkallweit1@...il.com; linux@...linux.org.uk; davem@...emloft.net;
> kuba@...nel.org; pabeni@...hat.com; p.zabel@...gutronix.de;
> devicetree@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> linux-aspeed@...ts.ozlabs.org; linux-kernel@...r.kernel.org;
> netdev@...r.kernel.org; BMC-SW <BMC-SW@...eedtech.com>
> Subject: Re: [PATCH 0/2] Add reset deassertion for Aspeed MDIO
> 
> On Mon, Mar 21, 2022 at 03:01:29PM +0800, Dylan Hung wrote:
> > Add missing reset deassertion for Aspeed MDIO. There are 4 MDIOs
> > embedded in Aspeed AST2600 and share one reset control bit SCU50[3].
> 
> Is the reset limited to the MDIO bus masters, or are PHYs one the bus
> potentially also reset?

It is limited to the MDIO bus masters.

> 
> Who asserts the reset in the first place? 

The hardware asserts the reset by default.

> Don't you want the first MDIO bus to
> probe to assert and then deassert the reset in order that all the hardware is
> reset?

Do I still need to add a reset assertion/deassertion if the hardware asserts the reset by default?

> 
>     Andrew

--
Dylan