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Message-ID: <Ykwze3+VW4LtBb7j@lunn.ch>
Date:   Tue, 5 Apr 2022 14:18:03 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Andy Chiu <andy.chiu@...ive.com>
Cc:     davem@...emloft.net, michal.simek@...inx.com,
        radhey.shyam.pandey@...inx.com, kuba@...nel.org, pabeni@...hat.com,
        robh+dt@...nel.org, krzk+dt@...nel.org, linux@...linux.org.uk,
        netdev@...r.kernel.org, devicetree@...r.kernel.org,
        Greentime Hu <greentime.hu@...ive.com>,
        Rob Herring <robh@...nel.org>
Subject: Re: [PATCH v8 net-next 3/4] dt-bindings: net: add pcs-handle
 attribute

On Tue, Apr 05, 2022 at 05:19:28PM +0800, Andy Chiu wrote:
> Document the new pcs-handle attribute to support connecting to an
> external PHY. For Xilinx's AXI Ethernet, this is used when the core
> operates in SGMII or 1000Base-X modes and links through the internal
> PCS/PMA PHY.
> 
> Signed-off-by: Andy Chiu <andy.chiu@...ive.com>
> Reviewed-by: Greentime Hu <greentime.hu@...ive.com>
> Reviewed-by: Rob Herring <robh@...nel.org>

Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew

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