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Message-Id: <20220429184432.962738-1-nate.d@variscite.com> Date: Fri, 29 Apr 2022 13:44:31 -0500 From: Nate Drude <nate.d@...iscite.com> To: netdev@...r.kernel.org Cc: michael.hennerich@...log.com, eran.m@...iscite.com, Nate Drude <nate.d@...iscite.com> Subject: [PATCH 1/2] dt-bindings: net: adin: document adi,clk_rcvr_125_en property Document device tree property to set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG), causing the 125 MHz PHY recovered clock (or PLL clock) to be driven at the GP_CLK pin. Signed-off-by: Nate Drude <nate.d@...iscite.com> --- Documentation/devicetree/bindings/net/adi,adin.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/adi,adin.yaml b/Documentation/devicetree/bindings/net/adi,adin.yaml index 1129f2b58e98..5fdbbd5aff82 100644 --- a/Documentation/devicetree/bindings/net/adi,adin.yaml +++ b/Documentation/devicetree/bindings/net/adi,adin.yaml @@ -36,6 +36,11 @@ properties: enum: [ 4, 8, 12, 16, 20, 24 ] default: 8 + adi,clk_rcvr_125_en: + description: | + Set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG), causing the 125 MHz + PHY recovered clock (or PLL clock) to be driven at the GP_CLK pin. + unevaluatedProperties: false examples: -- 2.25.1
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