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Date:   Fri, 29 Apr 2022 13:44:32 -0500
From:   Nate Drude <nate.d@...iscite.com>
To:     netdev@...r.kernel.org
Cc:     michael.hennerich@...log.com, eran.m@...iscite.com,
        Nate Drude <nate.d@...iscite.com>
Subject: [PATCH 2/2] net: phy: adin: add adi,clk_rcvr_125_en property

Add device tree property to set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG),
causing the 125 MHz PHY recovered clock (or PLL clock) to be driven at
the GP_CLK pin.

Signed-off-by: Nate Drude <nate.d@...iscite.com>
---
 drivers/net/phy/adin.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index 5ce6da62cc8e..600472341cef 100644
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -14,6 +14,7 @@
 #include <linux/mii.h>
 #include <linux/phy.h>
 #include <linux/property.h>
+#include <linux/of.h>
 
 #define PHY_ID_ADIN1200				0x0283bc20
 #define PHY_ID_ADIN1300				0x0283bc30
@@ -99,6 +100,9 @@
 #define ADIN1300_GE_SOFT_RESET_REG		0xff0c
 #define   ADIN1300_GE_SOFT_RESET		BIT(0)
 
+#define ADIN1300_GE_CLK_CFG			0xff1f
+#define   ADIN1300_GE_CLK_RCVR_125_EN		BIT(5)
+
 #define ADIN1300_GE_RGMII_CFG_REG		0xff23
 #define   ADIN1300_GE_RGMII_RX_MSK		GENMASK(8, 6)
 #define   ADIN1300_GE_RGMII_RX_SEL(x)		\
@@ -407,6 +411,27 @@ static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval)
 			  val);
 }
 
+static int adin_set_clock_config(struct phy_device *phydev)
+{
+	struct device *dev = &phydev->mdio.dev;
+	struct device_node *of_node = dev->of_node;
+	int reg = 0;
+
+	if (of_property_read_bool(of_node, "adi,clk_rcvr_125_en")) {
+		reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG);
+
+		reg |= ADIN1300_GE_CLK_RCVR_125_EN;
+
+		phydev_dbg(phydev, "%s: ADIN1300_GE_CLK_CFG = %x\n",
+		           __func__, reg);
+
+		reg = phy_write_mmd(phydev, MDIO_MMD_VEND1,
+			     ADIN1300_GE_CLK_CFG, reg);
+	}
+
+	return reg;
+}
+
 static int adin_get_tunable(struct phy_device *phydev,
 			    struct ethtool_tunable *tuna, void *data)
 {
@@ -455,6 +480,10 @@ static int adin_config_init(struct phy_device *phydev)
 	if (rc < 0)
 		return rc;
 
+	rc = adin_set_clock_config(phydev);
+	if (rc < 0)
+		return rc;
+
 	phydev_dbg(phydev, "PHY is using mode '%s'\n",
 		   phy_modes(phydev->interface));
 
-- 
2.25.1

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