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Message-ID: <YmxouZJPpdCXhtLJ@lunn.ch> Date: Sat, 30 Apr 2022 00:37:45 +0200 From: Andrew Lunn <andrew@...n.ch> To: Nate Drude <nate.d@...iscite.com> Cc: netdev@...r.kernel.org, michael.hennerich@...log.com, eran.m@...iscite.com Subject: Re: [PATCH 1/2] dt-bindings: net: adin: document adi,clk_rcvr_125_en property On Fri, Apr 29, 2022 at 01:44:31PM -0500, Nate Drude wrote: > Document device tree property to set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG), > causing the 125 MHz PHY recovered clock (or PLL clock) to be driven at > the GP_CLK pin. Hi Nate Have you seen: https://lore.kernel.org/netdev/20220419102709.26432-1-josua@solid-run.com/ Andrew
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