netdev - Re: [PATCH 1/2] dt-bindings: net: adin: document adi,clk_rcvr_125

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Message-ID: <a11501d365b3ee401116e0f77c16f6c2f63ef69b.camel@redhat.com>
Date:   Mon, 02 May 2022 11:03:35 +0200
From:   Paolo Abeni <pabeni@...hat.com>
To:     Nate Drude <nate.d@...iscite.com>, netdev@...r.kernel.org
Cc:     michael.hennerich@...log.com, eran.m@...iscite.com,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        devicetree@...r.kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: net: adin: document
 adi,clk_rcvr_125_en property

Hello,

On Fri, 2022-04-29 at 13:44 -0500, Nate Drude wrote:
> Document device tree property to set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG),
> causing the 125 MHz PHY recovered clock (or PLL clock) to be driven at
> the GP_CLK pin.
> 
> Signed-off-by: Nate Drude <nate.d@...iscite.com>
> ---
>  Documentation/devicetree/bindings/net/adi,adin.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/adi,adin.yaml b/Documentation/devicetree/bindings/net/adi,adin.yaml
> index 1129f2b58e98..5fdbbd5aff82 100644
> --- a/Documentation/devicetree/bindings/net/adi,adin.yaml
> +++ b/Documentation/devicetree/bindings/net/adi,adin.yaml
> @@ -36,6 +36,11 @@ properties:
>      enum: [ 4, 8, 12, 16, 20, 24 ]
>      default: 8
>  
> +  adi,clk_rcvr_125_en:
> +    description: |
> +      Set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG), causing the 125 MHz
> +      PHY recovered clock (or PLL clock) to be driven at the GP_CLK pin.
> +
>  unevaluatedProperties: false
>  
>  examples:

The recipients list does not contain a few required ones, adding for
awareness Rob, Krzysztof and the devicetree ML. If a new version should
be required, please include them.

Thanks!

Paolo