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Message-ID: <20220510183025.gvfxcep6mx4gdmr7@skbuf>
Date: Tue, 10 May 2022 21:30:25 +0300
From: Vladimir Oltean <olteanv@...il.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: netdev <netdev@...r.kernel.org>,
Sean Wang <sean.wang@...iatek.com>,
Landen Chao <Landen.Chao@...iatek.com>,
DENG Qingfang <dqfext@...il.com>,
Vivien Didelot <vivien.didelot@...il.com>,
Florian Fainelli <f.fainelli@...il.com>,
Matthias Brugger <matthias.bgg@...il.com>,
Joakim Zhang <qiangqing.zhang@....com>,
Sergey Shtylyov <s.shtylyov@....ru>,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
Tobias Waldekranz <tobias@...dekranz.com>,
Marcin Wojtas <mw@...ihalf.com>,
Calvin Johnson <calvin.johnson@....nxp.com>,
Markus Koch <markus@...syncing.net>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Yang Yingliang <yangyingliang@...wei.com>,
Hao Chen <chenhao288@...ilicon.com>
Subject: Re: [PATCH net-next 08/10] net: ethernet: freescale: fec: Separate
C22 and C45 transactions for xgmac
On Sun, May 08, 2022 at 05:30:47PM +0200, Andrew Lunn wrote:
> The fec MDIO bus driver can perform both C22 and C45 transfers.
> Create separate functions for each and register the C45 versions using
> the new API calls where appropriate.
>
> Signed-off-by: Andrew Lunn <andrew@...n.ch>
> ---
> drivers/net/ethernet/freescale/fec_main.c | 149 +++++++++++++++-------
> 1 file changed, 101 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
> index 9f33ec838b52..6f749387b5c5 100644
> --- a/drivers/net/ethernet/freescale/fec_main.c
> +++ b/drivers/net/ethernet/freescale/fec_main.c
> @@ -1860,47 +1860,74 @@ static int fec_enet_mdio_wait(struct fec_enet_private *fep)
> return ret;
> }
>
> -static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
> +static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
> {
> struct fec_enet_private *fep = bus->priv;
> struct device *dev = &fep->pdev->dev;
> int ret = 0, frame_start, frame_addr, frame_op;
> - bool is_c45 = !!(regnum & MII_ADDR_C45);
>
> ret = pm_runtime_resume_and_get(dev);
> if (ret < 0)
> return ret;
>
> - if (is_c45) {
> - frame_start = FEC_MMFR_ST_C45;
> + /* C22 read */
> + frame_op = FEC_MMFR_OP_READ;
> + frame_start = FEC_MMFR_ST;
> + frame_addr = regnum;
>
> - /* write address */
> - frame_addr = (regnum >> 16);
> - writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
> - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
> - FEC_MMFR_TA | (regnum & 0xFFFF),
> - fep->hwp + FEC_MII_DATA);
> + /* start a read op */
> + writel(frame_start | frame_op |
> + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
> + FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
You lost the argument alignment to the open parenthesis.
>
> - /* wait for end of transfer */
> - ret = fec_enet_mdio_wait(fep);
> - if (ret) {
> - netdev_err(fep->netdev, "MDIO address write timeout\n");
> - goto out;
> - }
> + /* wait for end of transfer */
> + ret = fec_enet_mdio_wait(fep);
> + if (ret) {
> + netdev_err(fep->netdev, "MDIO read timeout\n");
> + goto out;
> + }
>
> - frame_op = FEC_MMFR_OP_READ_C45;
> + ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
>
> - } else {
> - /* C22 read */
> - frame_op = FEC_MMFR_OP_READ;
> - frame_start = FEC_MMFR_ST;
> - frame_addr = regnum;
> +out:
> + pm_runtime_mark_last_busy(dev);
> + pm_runtime_put_autosuspend(dev);
> +
> + return ret;
> +}
> +
> +static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id,
> + int devad, int regnum)
> +{
> + struct fec_enet_private *fep = bus->priv;
> + struct device *dev = &fep->pdev->dev;
> + int ret = 0, frame_start, frame_op;
> +
> + ret = pm_runtime_resume_and_get(dev);
> + if (ret < 0)
> + return ret;
> +
> + frame_start = FEC_MMFR_ST_C45;
> +
> + /* write address */
> + writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
> + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
> + FEC_MMFR_TA | (regnum & 0xFFFF),
> + fep->hwp + FEC_MII_DATA);
> +
> + /* wait for end of transfer */
> + ret = fec_enet_mdio_wait(fep);
> + if (ret) {
> + netdev_err(fep->netdev, "MDIO address write timeout\n");
> + goto out;
> }
>
> + frame_op = FEC_MMFR_OP_READ_C45;
> +
> /* start a read op */
> writel(frame_start | frame_op |
> - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
> - FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
> + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
> + FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
>
> /* wait for end of transfer */
> ret = fec_enet_mdio_wait(fep);
> @@ -1918,43 +1945,67 @@ static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
> return ret;
> }
>
> -static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
> - u16 value)
> +static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
> + u16 value)
> {
> struct fec_enet_private *fep = bus->priv;
> struct device *dev = &fep->pdev->dev;
> int ret, frame_start, frame_addr;
> - bool is_c45 = !!(regnum & MII_ADDR_C45);
>
> ret = pm_runtime_resume_and_get(dev);
> if (ret < 0)
> return ret;
>
> - if (is_c45) {
> - frame_start = FEC_MMFR_ST_C45;
> + /* C22 write */
> + frame_start = FEC_MMFR_ST;
> + frame_addr = regnum;
>
> - /* write address */
> - frame_addr = (regnum >> 16);
> - writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
> - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
> - FEC_MMFR_TA | (regnum & 0xFFFF),
> - fep->hwp + FEC_MII_DATA);
> + /* start a write op */
> + writel(frame_start | FEC_MMFR_OP_WRITE |
> + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
> + FEC_MMFR_TA | FEC_MMFR_DATA(value),
> + fep->hwp + FEC_MII_DATA);
Here as well.
>
> - /* wait for end of transfer */
> - ret = fec_enet_mdio_wait(fep);
> - if (ret) {
> - netdev_err(fep->netdev, "MDIO address write timeout\n");
> - goto out;
> - }
> - } else {
> - /* C22 write */
> - frame_start = FEC_MMFR_ST;
> - frame_addr = regnum;
> + /* wait for end of transfer */
> + ret = fec_enet_mdio_wait(fep);
> + if (ret)
> + netdev_err(fep->netdev, "MDIO write timeout\n");
> +
> + pm_runtime_mark_last_busy(dev);
> + pm_runtime_put_autosuspend(dev);
> +
> + return ret;
> +}
> +
> +static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id,
> + int devad, int regnum, u16 value)
> +{
> + struct fec_enet_private *fep = bus->priv;
> + struct device *dev = &fep->pdev->dev;
> + int ret, frame_start;
> +
> + ret = pm_runtime_resume_and_get(dev);
> + if (ret < 0)
> + return ret;
> +
> + frame_start = FEC_MMFR_ST_C45;
> +
> + /* write address */
> + writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
> + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
> + FEC_MMFR_TA | (regnum & 0xFFFF),
> + fep->hwp + FEC_MII_DATA);
> +
> + /* wait for end of transfer */
> + ret = fec_enet_mdio_wait(fep);
> + if (ret) {
> + netdev_err(fep->netdev, "MDIO address write timeout\n");
> + goto out;
> }
>
> /* start a write op */
> writel(frame_start | FEC_MMFR_OP_WRITE |
> - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
> + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
> FEC_MMFR_TA | FEC_MMFR_DATA(value),
> fep->hwp + FEC_MII_DATA);
>
> @@ -2254,8 +2305,10 @@ static int fec_enet_mii_init(struct platform_device *pdev)
> }
>
> fep->mii_bus->name = "fec_enet_mii_bus";
> - fep->mii_bus->read = fec_enet_mdio_read;
> - fep->mii_bus->write = fec_enet_mdio_write;
> + fep->mii_bus->read = fec_enet_mdio_read_c22;
> + fep->mii_bus->write = fec_enet_mdio_write_c22;
> + fep->mii_bus->read_c45 = fec_enet_mdio_read_c45;
> + fep->mii_bus->write_c45 = fec_enet_mdio_write_c45;
> snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
> pdev->name, fep->dev_id + 1);
> fep->mii_bus->priv = fep;
> --
> 2.36.0
>
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