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Message-ID: <YrWdnQKVbJR+NrfH@lunn.ch>
Date:   Fri, 24 Jun 2022 13:18:53 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Sebastian Reichel <sebastian.reichel@...labora.com>
Cc:     Giuseppe Cavallaro <peppe.cavallaro@...com>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        Jose Abreu <joabreu@...opsys.com>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        netdev@...r.kernel.org, linux-rockchip@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        David Wu <david.wu@...k-chips.com>, kernel@...labora.com
Subject: Re: [PATCH 1/3] net: ethernet: stmmac: dwmac-rk: Disable delayline
 if it is invalid

> @@ -1422,7 +1420,7 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
>  
>  	ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
>  	if (ret) {
> -		bsp_priv->tx_delay = 0x30;
> +		bsp_priv->tx_delay = -1;
>  		dev_err(dev, "Can not read property: tx_delay.");
>  		dev_err(dev, "set tx_delay to 0x%x\n",
>  			bsp_priv->tx_delay);
> @@ -1433,7 +1431,7 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
>  
>  	ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
>  	if (ret) {
> -		bsp_priv->rx_delay = 0x10;
> +		bsp_priv->rx_delay = -1;
>  		dev_err(dev, "Can not read property: rx_delay.");
>  		dev_err(dev, "set rx_delay to 0x%x\n",
>  			bsp_priv->rx_delay);

rockchip-dwmac.yaml says:


  tx_delay:
    description: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
    $ref: /schemas/types.yaml#/definitions/uint32

  rx_delay:
    description: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
    $ref: /schemas/types.yaml#/definitions/uint32

So it seems to me you are changing the documented default. You cannot
do that, this is ABI.

   Andrew

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