netdev - Re: [PATCH net-next v2 04/35] [RFC] phy: fsl: Add Lynx 10G SerDes driver

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Message-ID: <YsW+4fm/613ByK09@matsya>
Date:   Wed, 6 Jul 2022 22:27:05 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     Sean Anderson <sean.anderson@...o.com>
Cc:     "David S . Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Madalin Bucur <madalin.bucur@....com>, netdev@...r.kernel.org,
        Russell King <linux@...linux.org.uk>,
        Paolo Abeni <pabeni@...hat.com>,
        linux-arm-kernel@...ts.infradead.org,
        Eric Dumazet <edumazet@...gle.com>,
        linux-kernel@...r.kernel.org,
        Ioana Ciornei <ioana.ciornei@....com>,
        Jonathan Corbet <corbet@....net>,
        Kishon Vijay Abraham I <kishon@...com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        linux-doc@...r.kernel.org, linux-phy@...ts.infradead.org
Subject: Re: [PATCH net-next v2 04/35] [RFC] phy: fsl: Add Lynx 10G SerDes
 driver

On 05-07-22, 11:29, Sean Anderson wrote:

> >> +	/* TODO: wait for the PLL to lock */
> > 
> > when will this be added?
> 
> I'm not sure. I haven't had any issues with this, and waiting on the lock bit is
> only mentioned in some datasheets for this SerDes. On the LS1046A for example,
> there is no mention of waiting for lock.

okay maybe remove the comment then?

> >> +static const struct clk_ops lynx_pll_clk_ops = {
> >> +	.enable = lynx_pll_enable,
> >> +	.disable = lynx_pll_disable,
> >> +	.is_enabled = lynx_pll_is_enabled,
> >> +	.recalc_rate = lynx_pll_recalc_rate,
> >> +	.round_rate = lynx_pll_round_rate,
> >> +	.set_rate = lynx_pll_set_rate,
> >> +};
> > 
> > right, this should be a clk driver
> 
> Well, it is a clock driver, effectively internal to the SerDes. There are a few
> examples of this already (e.g. the qualcomm and cadence phys). It could of course
> be split off, but I would prefer that they remained together.

I would prefer clk driver is split and we maintain clean split b/w phy
and clk

-- 
~Vinod