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Date:   Tue, 12 Jul 2022 14:56:23 +0200
From:   Marc Kleine-Budde <>
To:     Biju Das <>
Cc:     Wolfgang Grandegger <>,
        "David S. Miller" <>,
        Eric Dumazet <>,
        Jakub Kicinski <>,
        Paolo Abeni <>,,,
        Uwe Kleine-K├Ânig 
        Geert Uytterhoeven <>,
        Chris Paterson <>,
        Biju Das <>,
Subject: Re: [PATCH v4 6/6] can: sja1000: Add support for RZ/N1 SJA1000 CAN

On 10.07.2022 12:52:48, Biju Das wrote:
> The SJA1000 CAN controller on RZ/N1 SoC has no clock divider register
> (CDR) support compared to others.
> This patch adds support for RZ/N1 SJA1000 CAN Controller, by adding
> SoC specific compatible to handle this difference as well as using
> clk framework to retrieve the CAN clock frequency.
> Signed-off-by: Biju Das <>
> ---
> v3->v4:
>  * Updated commit description.
>  * Updated clock handling as per bindings.
> v2->v3:
>  * No change.
> v1->v2:
>  * Updated commit description as SJA1000_NO_HW_LOOPBACK_QUIRK is removed
>  * Added error handling on clk error path
>  * Started using "devm_clk_get_optional_enabled" for clk get,prepare and enable.

Due to the use of the devm_clk_get_optional_enabled(), this patch has to
wait until devm_clk_get_optional_enabled() hits net-next/master, which
will be probably for the v5.21 merge window.

We either have to wait or you have to manually enable and disable the


Pengutronix e.K.                 | Marc Kleine-Budde           |
Embedded Linux                   |  |
Vertretung West/Dortmund         | Phone: +49-231-2826-924     |
Amtsgericht Hildesheim, HRA 2686 | Fax:   +49-5121-206917-5555 |

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