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Message-ID: <20220718105128.s22vp5hx4somy64f@pengutronix.de>
Date: Mon, 18 Jul 2022 12:51:28 +0200
From: Marc Kleine-Budde <mkl@...gutronix.de>
To: Pavel Pisa <pisa@....felk.cvut.cz>
Cc: Matej Vasilevski <matej.vasilevski@...nam.cz>,
Appana Durga Kedareswara rao <appana.durga.rao@...inx.com>,
Naga Sureshkumar Relli <naga.sureshkumar.relli@...inx.com>,
Wolfgang Grandegger <wg@...ndegger.com>,
linux-can@...r.kernel.org, netdev@...r.kernel.org,
Martin Jerabek <martin.jerabek01@...il.com>,
Vikram Garhwal <fnu.vikram@...inx.com>
Subject: Re: [PATCH] can: xilinx_can: add support for RX timestamps on Zynq
On 18.07.2022 12:20:06, Pavel Pisa wrote:
> Hello Marc,
>
> On Monday 18 of July 2022 10:33:12 Marc Kleine-Budde wrote:
> > On 16.07.2022 14:04:09, Matej Vasilevski wrote:
> > > This patch adds support for hardware RX timestamps from Xilinx Zynq CAN
> > > controllers. The timestamp is calculated against a timepoint reference
> > > stored when the first CAN message is received.
> > >
> > > When CAN bus traffic does not contain long idle pauses (so that
> > > the clocks would drift by a multiple of the counter rollover time),
> > > then the hardware timestamps provide precise relative time between
> > > received messages. This can be used e.g. for latency testing.
> >
> > Please make use of the existing cyclecounter/timecounter framework. Is
> > there a way to read the current time from a register? If so, please
> > setup a worker that does that regularly.
> >
> > Have a look at the mcp251xfd driver as an example:
>
> Matej Vasilevski has looked at the example. But there is problem
> that we know no method how to read actual counter value at least for
> Xilinx Zynq 7000. May be we overlooked something or there
> is hidden test register.
I haven't found a documented register in the TRM. I've added Michal
Simek into the loop, maybe Michal has some connection to the HW
designers.
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
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