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Message-ID: <1659123350-10638-3-git-send-email-radhey.shyam.pandey@amd.com> Date: Sat, 30 Jul 2022 01:05:50 +0530 From: Radhey Shyam Pandey <radhey.shyam.pandey@....com> To: <michal.simek@...inx.com>, <nicolas.ferre@...rochip.com>, <claudiu.beznea@...rochip.com>, <davem@...emloft.net>, <edumazet@...gle.com>, <kuba@...nel.org>, <pabeni@...hat.com>, <gregkh@...uxfoundation.org> CC: <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>, <git@....com>, <git@...inx.com>, "Radhey Shyam Pandey" <radhey.shyam.pandey@....com> Subject: [PATCH v2 net-next 2/2] net: macb: Add zynqmp SGMII dynamic configuration support Add support for the dynamic configuration which takes care of configuring the GEM secure space configuration registers using EEMI APIs. High level sequence is to: - Check for the PM dynamic configuration support, if no error proceed with GEM dynamic configurations(next steps) otherwise skip the dynamic configuration. - Configure GEM Fixed configurations. - Configure GEM_CLK_CTRL (gemX_sgmii_mode). - Trigger GEM reset. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@....com> Reviewed-by: Andrew Lunn <andrew@...n.ch> Tested-by: Conor Dooley <conor.dooley@...rochip.com> (for MPFS) --- Changes for v2: - Add phy_exit() in error return paths. --- drivers/net/ethernet/cadence/macb_main.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 4cd4f57ca2aa..517b40ff098b 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -38,6 +38,7 @@ #include <linux/pm_runtime.h> #include <linux/ptp_classify.h> #include <linux/reset.h> +#include <linux/firmware/xlnx-zynqmp.h> #include "macb.h" /* This structure is only used for MACB on SiFive FU540 devices */ @@ -4621,6 +4622,30 @@ static int init_reset_optional(struct platform_device *pdev) "failed to init SGMII PHY\n"); } + ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_GEM_CONFIG); + if (!ret) { + u32 pm_info[2]; + + ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains", + pm_info, ARRAY_SIZE(pm_info)); + if (ret < 0) { + phy_exit(bp->sgmii_phy); + dev_err(&pdev->dev, "Failed to read power management information\n"); + return ret; + } + ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_FIXED, 0); + if (ret < 0) { + phy_exit(bp->sgmii_phy); + return ret; + } + + ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_SGMII_MODE, 1); + if (ret < 0) { + phy_exit(bp->sgmii_phy); + return ret; + } + } + /* Fully reset controller at hardware level if mapped in device tree */ ret = device_reset_optional(&pdev->dev); if (ret) { -- 2.1.1
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