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Message-ID: <20221101163453.jtouqmz3m6hrnftz@lion.mk-sys.cz>
Date: Tue, 1 Nov 2022 17:34:53 +0100
From: Michal Kubecek <mkubecek@...e.cz>
To: Vladimir Oltean <vladimir.oltean@....com>
Cc: netdev@...r.kernel.org, Claudiu Manoil <claudiu.manoil@....com>
Subject: Re: [PATCH ethtool] fsl_enetc: add support for NXP ENETC driver
On Wed, Oct 26, 2022 at 10:05:52PM +0300, Vladimir Oltean wrote:
> Add pretty printer for the registers which the enetc PF and VF drivers
> support since their introduction in kernel v5.1. The selection of
> registers parsed is the selection exported by the kernel as of v6.1-rc2.
> Unparsed registers are printed as raw.
>
> One register is printed field by field (MAC COMMAND_CONFIG), I didn't
> have time/interest in printing more than 1. The rest are printed in hex.
>
> Sample output:
>
> $ ethtool -d eno0
> SI mode register: 0x80000000
> SI primary MAC address register 0: 0x59f0400
> SI primary MAC address register 1: 0x27f6
> SI control BDR mode register: 0x40000000
> SI control BDR status register: 0x0
> SI control BDR base address register 0: 0x8262f000
> SI control BDR base address register 1: 0x20
> SI control BDR producer index register: 0x3a
> SI control BDR consumer index register: 0x3a
> SI control BDR length register: 0x40
> SI capability register 0: 0x10080008
> SI capability register 1: 0x20002
> SI uncorrectable error frame drop count register: 0x0
> TX BDR 0 mode register: 0x80000200
> TX BDR 0 status register: 0x0
> TX BDR 0 base address register 0: 0xebfa0000
> TX BDR 0 base address register 1: 0x0
> TX BDR 0 producer index register: 0x12
> TX BDR 0 consumer index register: 0x12
> TX BDR 0 length register: 0x800
> TX BDR 0 interrupt enable register: 0x1
> TX BDR 0 interrupt coalescing register 0: 0x80000008
> TX BDR 0 interrupt coalescing register 1: 0x3a980
> (repeats for other TX rings)
> RX BDR 0 mode register: 0x80000034
> RX BDR 0 status register: 0x0
> RX BDR 0 buffer size register: 0x680
> RX BDR 0 consumer index register: 0x7ff
> RX BDR 0 base address register 0: 0xec430000
> RX BDR 0 base address register 1: 0x0
> RX BDR 0 producer index register: 0x0
> RX BDR 0 length register: 0x800
> RX BDR 0 interrupt enable register: 0x1
> RX BDR 0 interrupt coalescing register 0: 0x80000100
> RX BDR 0 interrupt coalescing register 1: 0x1
> (repeats for other RX rings)
> Port mode register: 0x70200
> Port status register: 0x0
> Port SI promiscuous mode register: 0x0
> Port SI0 primary MAC address register 0: 0x59f0400
> Port SI0 primary MAC address register 1: 0x27f6
> Port HTA transmit memory buffer allocation register: 0xc390
> Port capability register 0: 0x10101b3c
> Port capability register 1: 0x2070
> Port SI0 configuration register 0: 0x3080008
> Port RFS capability register: 0x2
> Port traffic class 0 maximum SDU register: 0x2580
> Port eMAC Command and Configuration Register: 0x8813
> MG 0
> RXSTP 0
> REG_LOWP_RXETY 0
> TX_LOWP_ENA 0
> SFD 0
> NO_LEN_CHK 0
> SEND_IDLE 0
> CNT_FRM_EN 0
> SWR 0
> TXP 1
> XGLP 0
> TX_ADDR_INS 0
> PAUSE_IGN 0
> PAUSE_FWD 0
> CRC 0
> PAD 0
> PROMIS 1
> WAN 0
> RX_EN 1
> TX_EN 1
> Port eMAC Maximum Frame Length Register: 0x2580
> Port eMAC Interface Mode Control Register: 0x1002
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@....com>
Looks good to me, just a cosmetic issue below.
[...]
> diff --git a/fsl_enetc.c b/fsl_enetc.c
> new file mode 100644
> index 000000000000..c39f5cb3ce3f
> --- /dev/null
> +++ b/fsl_enetc.c
> @@ -0,0 +1,259 @@
> +/* Code to dump registers for the Freescale/NXP ENETC controller.
> + *
> + * Copyright 2022 NXP
> + */
> +#include <stdio.h>
> +#include "internal.h"
> +
> +#define BIT(x) (1 << (x))
This macro is only used to mask bits of a u32 value, wouldn't "1U" be
more appropriate?
Michal
[...]
> +#define ENETC_PM0_CMD_TX_EN BIT(0)
> +#define ENETC_PM0_CMD_RX_EN BIT(1)
> +#define ENETC_PM0_CMD_WAN BIT(3)
> +#define ENETC_PM0_CMD_PROMISC BIT(4)
> +#define ENETC_PM0_CMD_PAD BIT(5)
> +#define ENETC_PM0_CMD_CRC BIT(6)
> +#define ENETC_PM0_CMD_PAUSE_FWD BIT(7)
> +#define ENETC_PM0_CMD_PAUSE_IGN BIT(8)
> +#define ENETC_PM0_CMD_TX_ADDR_INS BIT(9)
> +#define ENETC_PM0_CMD_XGLP BIT(10)
> +#define ENETC_PM0_CMD_TXP BIT(11)
> +#define ENETC_PM0_CMD_SWR BIT(12)
> +#define ENETC_PM0_CMD_CNT_FRM_EN BIT(13)
> +#define ENETC_PM0_CMD_SEND_IDLE BIT(16)
> +#define ENETC_PM0_CMD_NO_LEN_CHK BIT(17)
> +#define ENETC_PM0_CMD_SFD BIT(21)
> +#define ENETC_PM0_CMD_TX_LOWP_ENA BIT(23)
> +#define ENETC_PM0_CMD_REG_LOWP_RXETY BIT(24)
> +#define ENETC_PM0_CMD_RXSTP BIT(29)
> +#define ENETC_PM0_CMD_MG BIT(31)
[...]
> +static void decode_cmd_cfg(u32 val, char *buf)
> +{
> + sprintf(buf, "\tMG %d\n\tRXSTP %d\n\tREG_LOWP_RXETY %d\n"
> + "\tTX_LOWP_ENA %d\n\tSFD %d\n\tNO_LEN_CHK %d\n\tSEND_IDLE %d\n"
> + "\tCNT_FRM_EN %d\n\tSWR %d\n\tTXP %d\n\tXGLP %d\n"
> + "\tTX_ADDR_INS %d\n\tPAUSE_IGN %d\n\tPAUSE_FWD %d\n\tCRC %d\n"
> + "\tPAD %d\n\tPROMIS %d\n\tWAN %d\n\tRX_EN %d\n\tTX_EN %d\n",
> + !!(val & ENETC_PM0_CMD_MG),
> + !!(val & ENETC_PM0_CMD_RXSTP),
> + !!(val & ENETC_PM0_CMD_REG_LOWP_RXETY),
> + !!(val & ENETC_PM0_CMD_TX_LOWP_ENA),
> + !!(val & ENETC_PM0_CMD_SFD),
> + !!(val & ENETC_PM0_CMD_NO_LEN_CHK),
> + !!(val & ENETC_PM0_CMD_SEND_IDLE),
> + !!(val & ENETC_PM0_CMD_CNT_FRM_EN),
> + !!(val & ENETC_PM0_CMD_SWR),
> + !!(val & ENETC_PM0_CMD_TXP),
> + !!(val & ENETC_PM0_CMD_XGLP),
> + !!(val & ENETC_PM0_CMD_TX_ADDR_INS),
> + !!(val & ENETC_PM0_CMD_PAUSE_IGN),
> + !!(val & ENETC_PM0_CMD_PAUSE_FWD),
> + !!(val & ENETC_PM0_CMD_CRC),
> + !!(val & ENETC_PM0_CMD_PAD),
> + !!(val & ENETC_PM0_CMD_PROMISC),
> + !!(val & ENETC_PM0_CMD_WAN),
> + !!(val & ENETC_PM0_CMD_RX_EN),
> + !!(val & ENETC_PM0_CMD_TX_EN));
> +}
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