netdev - Re: [PATCH net] stmmac: fix potential division by 0

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Message-ID: <Y5EvKciMg3Nkj8ln@lunn.ch>
Date:   Thu, 8 Dec 2022 01:26:17 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Kurt Kanzenbach <kurt@...utronix.de>
Cc:     Jakub Kicinski <kuba@...nel.org>,
        Piergiorgio Beruto <piergiorgio.beruto@...il.com>,
        netdev@...r.kernel.org, peppe.cavallaro@...com,
        Voon Weifeng <weifeng.voon@...el.com>,
        Rayagond Kokatanur <rayagond@...avyalabs.com>,
        Jose Abreu <Jose.Abreu@...opsys.com>,
        Antonio Borneo <antonio.borneo@...com>,
        Tan Tee Min <tee.min.tan@...el.com>
Subject: Re: [PATCH net] stmmac: fix potential division by 0

On Wed, Dec 07, 2022 at 03:50:13PM +0100, Kurt Kanzenbach wrote:
> On Wed Dec 07 2022, Andrew Lunn wrote:
> > On Tue, Dec 06, 2022 at 06:28:23PM -0800, Jakub Kicinski wrote:
> >> On Thu, 1 Dec 2022 15:49:37 +0100 Andrew Lunn wrote:
> >> > > The root cause is the MAC using the internal clock as a PTP reference
> >> > > (default), which should be allowed since the connection to an external
> >> > > PTP clock is optional from an HW perspective. The internal clock seems
> >> > > to be derived from the MII clock speed, which is 2.5 MHz at 10 Mb/s.  
> >> > 
> >> > I think we need help from somebody who understands PTP on this device.
> >> > The clock is clearly out of range, but how important is that to PTP?
> >> > Will PTP work if the value is clamped to 0xff? Or should we be
> >> > returning -EINVAL and disabling PTP because it has no chance of
> >> > working?
> >> 
> >> Indeed, we need some more info here :( Like does the PTP actually
> >> work with 2.5 MHz clock? The frequency adjustment only cares about 
> >> the addend, what is sub_second_inc thing?
> >
> > Hi Jakub
> >
> > I Cc: many of the people who worked on PTP with this hardware, and
> > nobody has replied.
> >
> > I think we should wait a couple more days, and then add a range check,
> > and disable PTP for invalid clocks. That might provoke feedback.
> 
> Here's the Altera manual:
> 
>  https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/functional-description-of-the-emac.html
> 
> Table 183 shows the minimum PTP frequencies and also states "Therefore,
> a higher PTP clock frequency gives better system performance.".
> 
> So, I'd say using a clock of 2.5MHz seems possible, but will result in
> suboptimal precision.

Thanks for the info. So i seems like the correct fix is to camp to
0xff, rather than mask with 0xff.

      Andrew