netdev - Re: mv88e6321, dual cpu port

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Message-ID: <Y+D/lYul5X0JuHOR@lunn.ch>
Date:   Mon, 6 Feb 2023 14:24:37 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Angelo Dureghello <angelo@...nel-space.org>
Cc:     Vladimir Oltean <olteanv@...il.com>, netdev@...r.kernel.org
Subject: Re: mv88e6321, dual cpu port

> This is what i am testing now, a bit different,
> swapped ports 5 and 6.
> 
> #
> # Configuration:
> #                                   cpu      +---- port0
> #              br0 eth0  <-> rgmii  port 6  -+---- port1
> #                                            |
> #                                            +---- port2
> #
> #                                  user      +---- port3
> #              br1 eth1  <-> rmii  port 5   -+-----port4
> #
> #
> 
> mdio {
> 		#address-cells = <1>;
> 		#size-cells = <0>;
> 
> 		switch1: switch1@1d {
> 			compatible = "marvell,mv88e6085";
> 			reg = <0x1d>;
> 			interrupt-parent = <&lsio_gpio3>;
> 			interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
> 			interrupt-controller;
> 			#interrupt-cells = <2>;
> 
> 			ports {
> 				#address-cells = <1>;
> 				#size-cells = <0>;
> 
> 				port@0 {
> 					reg = <0>;
> 					label = "port0";
> 					phy-mode = "1000base-x";
> 					managed = "in-band-status";
> 					sfp = <&sfp_0>;
> 				};
> 				port@1 {
> 					reg = <1>;
> 					label = "port1";
> 					phy-mode = "1000base-x";
> 					managed = "in-band-status";
> 					sfp = <&sfp_1>;
> 				};
> 				/* This is phyenet0 now */
> 				port@2 {
> 					reg = <2>;
> 					label = "port2";
> 					phy-handle = <&switchphy2>;
> 				};
> 				port@6 {
> 					/* wired to cpu fec1 */
> 					reg = <6>;
> 					label = "cpu";
> 					ethernet = <&fec1>;
> 					fixed-link = <0 1 1000 0 0>;

This is the deprecated way to do fixed link. Use

                fixed-link {
                        speed = <1000>;
                        full-duplex;
                };


> 				};
> 				port@3 {
> 					/* phy is internal to the switch */
> 					reg = <3>;
> 					label = "port3";
> 					phy-handle = <&switchphy3>;
> 				};
> 				port@4 {
> 					/* phy is internal to the switch */
> 					reg = <4>;
> 					label = "port4";
> 					phy-handle = <&switchphy4>;
> 				};
> 				port@5 {
> 					/* wired to cpu fec2 */
> 					reg = <5>;
> 					label = "port5";
> 					ethernet = <&fec2>;

This is wrong. As far as the switch is concerned, this port is nothing
special. It is just a regular user port. So it should not have an
ethernet property.



> 					fixed-link = <1 1 100 0 0>;
> 				};
> 			};
> 
> All seems to work properly, but on ports 0, 1, 2 i cannot go
> over 100Mbit even if master port (6) is rgmii
> (testing by iperf3).

What SoC is this? Some FECs are only Fast ethernet.

What does ethtool show for eth0?

Do you also have a fixed link in the fec node?

   Andrew