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Message-ID: <20230208220309.4ekk4xpmpx27rkt6@skbuf>
Date:   Thu, 9 Feb 2023 00:03:09 +0200
From:   Vladimir Oltean <olteanv@...il.com>
To:     Clément Léger <clement.leger@...tlin.com>
Cc:     Andrew Lunn <andrew@...n.ch>,
        Florian Fainelli <f.fainelli@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Herve Codina <herve.codina@...tlin.com>,
        Miquèl Raynal <miquel.raynal@...tlin.com>,
        Milan Stevanovic <milan.stevanovic@...com>,
        Jimmy Lalande <jimmy.lalande@...com>,
        Pascal Eberhard <pascal.eberhard@...com>,
        Arun Ramadoss <Arun.Ramadoss@...rochip.com>,
        linux-renesas-soc@...r.kernel.org, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next v3 3/3] net: dsa: rzn1-a5psw: add vlan support

On Wed, Feb 08, 2023 at 05:17:49PM +0100, Clément Léger wrote:
> +static void a5psw_port_vlan_tagged_cfg(struct a5psw *a5psw, int vlan_res_id,
> +				       int port, bool set)
> +{
> +	u32 mask = A5PSW_VLAN_RES_WR_PORTMASK | A5PSW_VLAN_RES_RD_TAGMASK |
> +		   BIT(port);
> +	u32 vlan_res_off = A5PSW_VLAN_RES(vlan_res_id);
> +	u32 val = A5PSW_VLAN_RES_WR_TAGMASK, reg;
> +
> +	if (set)
> +		val |= BIT(port);
> +
> +	/* Toggle tag mask read */
> +	a5psw_reg_writel(a5psw, vlan_res_off, A5PSW_VLAN_RES_RD_TAGMASK);
> +	reg = a5psw_reg_readl(a5psw, vlan_res_off);
> +	a5psw_reg_writel(a5psw, vlan_res_off, A5PSW_VLAN_RES_RD_TAGMASK);

Is it intentional that this register is written twice?

> +
> +	reg &= ~mask;
> +	reg |= val;
> +	a5psw_reg_writel(a5psw, vlan_res_off, reg);
> +}

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