netdev - Re: [PATCH v5 14/19] clk: mediatek: Add MT8188 vencsys clock support

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Date:   Thu, 9 Mar 2023 05:28:15 +0000
From:   Garmin Chang (張家銘) 
        <Garmin.Chang@...iatek.com>
To:     "wenst@...omium.org" <wenst@...omium.org>
CC:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mturquette@...libre.com" <mturquette@...libre.com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "sboyd@...nel.org" <sboyd@...nel.org>,
        "linux-mediatek@...ts.infradead.org" 
        <linux-mediatek@...ts.infradead.org>,
        Project_Global_Chrome_Upstream_Group 
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        "richardcochran@...il.com" <richardcochran@...il.com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "matthias.bgg@...il.com" <matthias.bgg@...il.com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: Re: [PATCH v5 14/19] clk: mediatek: Add MT8188 vencsys clock support

On Fri, 2023-02-03 at 15:25 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:55 PM Garmin.Chang <
> Garmin.Chang@...iatek.com> wrote:
> > 
> > Add MT8188 vencsys clock controllers which provide clock gate
> > control for video encoder.
> > 
> > Signed-off-by: Garmin.Chang <Garmin.Chang@...iatek.com>
> > ---
> >  drivers/clk/mediatek/Makefile          |  2 +-
> >  drivers/clk/mediatek/clk-mt8188-venc.c | 52
> > ++++++++++++++++++++++++++
> >  2 files changed, 53 insertions(+), 1 deletion(-)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8188-venc.c
> > 
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index c654f4288e09..22a3840160fc 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -87,7 +87,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-
> > apmixedsys.o clk-mt8188-topckgen.o
> >                                    clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> >                                    clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> >                                    clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o \
> > -                                  clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o
> > +                                  clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> >  obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-venc.c
> > b/drivers/clk/mediatek/clk-mt8188-venc.c
> > new file mode 100644
> > index 000000000000..375ef99e2349
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-venc.c
> > @@ -0,0 +1,52 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@...iatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs ven1_cg_regs = {
> 
> Like the vdecsys patch, please change "ven" to "venc" to be
> consistent
> with usages elsewhere.


Thank you for your suggestions.
OK, I will modify this series in v6.
> 
> > +       .set_ofs = 0x4,
> > +       .clr_ofs = 0x8,
> > +       .sta_ofs = 0x0,
> > +};
> > +
> > +#define GATE_VEN1(_id, _name, _parent, _shift)                 \
> > +       GATE_MTK(_id, _name, _parent, &ven1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr_inv)
> > +
> > +static const struct mtk_gate ven1_clks[] = {
> > +       GATE_VEN1(CLK_VEN1_CKE0_LARB, "ven1_cke0_larb", "top_venc",
> > 0),
> > +       GATE_VEN1(CLK_VEN1_CKE1_VENC, "ven1_cke1_venc", "top_venc",
> > 4),
> > +       GATE_VEN1(CLK_VEN1_CKE2_JPGENC, "ven1_cke2_jpgenc",
> > "top_venc", 8),
> > +       GATE_VEN1(CLK_VEN1_CKE3_JPGDEC, "ven1_cke3_jpgdec",
> > "top_venc", 12),
> > +       GATE_VEN1(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_cke4_jpgdec_c1",
> > "top_venc", 16),
> > +       GATE_VEN1(CLK_VEN1_CKE5_GALS, "ven1_cke5_gals", "top_venc",
> > 28),
> > +       GATE_VEN1(CLK_VEN1_CKE6_GALS_SRAM, "ven1_cke6_gals_sram",
> > "top_venc", 31),
> 
> Is ckeN in both the macro name and clock name necessary? We don't
> really
> care about the index.
> 
> ChenYu

OK, I will modify it in v6.
> 
> > +};
> > +
> > +static const struct mtk_clk_desc ven1_desc = {
> > +       .clks = ven1_clks,
> > +       .num_clks = ARRAY_SIZE(ven1_clks),
> > +};
> > +
> > +static const struct of_device_id of_match_clk_mt8188_ven1[] = {
> > +       { .compatible = "mediatek,mt8188-vencsys", .data =
> > &ven1_desc },
> > +       { /* sentinel */ }
> > +};
> > +
> > +static struct platform_driver clk_mt8188_ven1_drv = {
> > +       .probe = mtk_clk_simple_probe,
> > +       .remove = mtk_clk_simple_remove,
> > +       .driver = {
> > +               .name = "clk-mt8188-ven1",
> > +               .of_match_table = of_match_clk_mt8188_ven1,
> > +       },
> > +};
> > +
> > +builtin_platform_driver(clk_mt8188_ven1_drv);
> > +MODULE_LICENSE("GPL");
> > --
> > 2.18.0
> > 
> >