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Message-ID: <4d9c562eb980642381cb43f65efb2ee13d742485.camel@mediatek.com>
Date: Sun, 26 Mar 2023 18:13:49 +0000
From: Landen Chao (趙皎宏)
<Landen.Chao@...iatek.com>
To: "olteanv@...il.com" <olteanv@...il.com>,
"andrew@...n.ch" <andrew@...n.ch>,
"arinc9.unal@...il.com" <arinc9.unal@...il.com>,
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Sean Wang <Sean.Wang@...iatek.com>,
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<angelogioacchino.delregno@...labora.com>
CC: "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"erkin.bozoglu@...ont.com" <erkin.bozoglu@...ont.com>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
"arinc.unal@...nc9.com" <arinc.unal@...nc9.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>
Subject: Re: [PATCH net 2/3] net: dsa: mt7530: move lowering TRGMII driving to
mt7530_setup()
On Mon, 2023-03-20 at 22:05 +0300, arinc9.unal@...il.com wrote:
>
> I asked this before, MT7530 DSA driver maintainers, please explain
> the code
> I mentioned on the second paragraph.
>
> ---
> @@ -2207,6 +2198,15 @@ mt7530_setup(struct dsa_switch *ds)
>
> mt7530_pll_setup(priv);
>
> + /* Lower Tx driving for TRGMII path */
> + for (i = 0; i < NUM_TRGMII_CTRL; i++)
> + mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
> + TD_DM_DRVP(8) | TD_DM_DRVN(8));
> +
I guess you ask this part, and I try my best to recall what the
original author said years ago.
It is used to adjust the RX delay of port 6 to match the tx
signal of the link partner.
> + for (i = 0; i < NUM_TRGMII_CTRL; i++)
> + mt7530_rmw(priv, MT7530_TRGMII_RD(i),
> + RD_TAP_MASK, RD_TAP(16));
> +
>
>
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