netdev - Re: [PATCH] net: fec: make use of MDIO C45 quirk

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Date:   Tue, 4 Apr 2023 15:23:47 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Greg Ungerer <gerg@...ux-m68k.org>
Cc:     wei.fang@....com, shenwei.wang@....com, xiaoning.wang@....com,
        linux-imx@....com, netdev@...r.kernel.org
Subject: Re: [PATCH] net: fec: make use of MDIO C45 quirk

On Tue, Apr 04, 2023 at 03:22:07PM +1000, Greg Ungerer wrote:
> Not all fec MDIO bus drivers support C45 mode transactions. The older fec
> hardware block in many ColdFire SoCs does not appear to support them, at
> least according to most of the different ColdFire SoC reference manuals.
> The bits used to generate C45 access on the iMX parts, in the OP field
> of the MMFR register, are documented as generating non-compliant MII
> frames (it is not documented as to exactly how they are non-compliant).
> 
> Commit 8d03ad1ab0b0 ("net: fec: Separate C22 and C45 transactions")
> means the fec driver will always register c45 MDIO read and write
> methods. During probe these will always be accessed now generating
> non-compliant MII accesses on ColdFire based devices.
> 
> Add a quirk define, FEC_QUIRK_HAS_MDIO_C45, that can be used to
> distinguish silicon that supports MDIO C45 framing or not. Add this to
> all the existing iMX quirks, so they will be behave as they do now (*).
> 
> (*) it seems that some iMX parts may not support C45 transactions either.
>     The iMX25 and iMX50 Reference Manuals contain similar wording to
>     the ColdFire Reference Manuals on this.
> 
> Fixes: 8d03ad1ab0b0 ("net: fec: Separate C22 and C45 transactions")
> Signed-off-by: Greg Ungerer <gerg@...ux-m68k.org>

Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew