netdev - [PATCH] phy: smsc: Implement .aneg

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Message-Id: <20230406131127.383006-1-lukma@denx.de>
Date:   Thu,  6 Apr 2023 15:11:27 +0200
From:   Lukasz Majewski <lukma@...x.de>
To:     Andrew Lunn <andrew@...n.ch>,
        Heiner Kallweit <hkallweit1@...il.com>
Cc:     Eric Dumazet <edumazet@...gle.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Russell King <linux@...linux.org.uk>,
        Paolo Abeni <pabeni@...hat.com>, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org, Lukasz Majewski <lukma@...x.de>
Subject: [PATCH] phy: smsc: Implement .aneg_done callback for LAN8720Ai

The LAN8720Ai has special bit (12) in the PHY SPECIAL
CONTROL/STATUS REGISTER (dec 31) to indicate if the
AutoNeg is finished.

Signed-off-by: Lukasz Majewski <lukma@...x.de>
---
 drivers/net/phy/smsc.c  | 8 ++++++++
 include/linux/smscphy.h | 2 ++
 2 files changed, 10 insertions(+)

diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c
index ac7481ce2fc1..58e5f06ef453 100644
--- a/drivers/net/phy/smsc.c
+++ b/drivers/net/phy/smsc.c
@@ -83,6 +83,13 @@ static int smsc_phy_config_intr(struct phy_device *phydev)
 	return rc < 0 ? rc : 0;
 }
 
+static int smsc_phy_aneg_done(struct phy_device *phydev)
+{
+	int rc = phy_read(phydev, MII_LAN83C185_PHY_CTRL_STS);
+
+	return rc & MII_LAN87XX_AUTODONE;
+}
+
 static irqreturn_t smsc_phy_handle_interrupt(struct phy_device *phydev)
 {
 	struct smsc_phy_priv *priv = phydev->priv;
@@ -416,6 +423,7 @@ static struct phy_driver smsc_phy_driver[] = {
 	.config_init	= smsc_phy_config_init,
 	.soft_reset	= smsc_phy_reset,
 	.config_aneg	= lan95xx_config_aneg_ext,
+	.aneg_done      = smsc_phy_aneg_done,
 
 	/* IRQ related */
 	.config_intr	= smsc_phy_config_intr,
diff --git a/include/linux/smscphy.h b/include/linux/smscphy.h
index 1a136271ba6a..0debebe999d6 100644
--- a/include/linux/smscphy.h
+++ b/include/linux/smscphy.h
@@ -4,6 +4,7 @@
 
 #define MII_LAN83C185_ISF 29 /* Interrupt Source Flags */
 #define MII_LAN83C185_IM  30 /* Interrupt Mask */
+#define MII_LAN83C185_PHY_CTRL_STS  31 /* PHY Special Control/Status Register */
 #define MII_LAN83C185_CTRL_STATUS 17 /* Mode/Status Register */
 #define MII_LAN83C185_SPECIAL_MODES 18 /* Special Modes Register */
 
@@ -22,6 +23,7 @@
 	 MII_LAN83C185_ISF_INT7)
 
 #define MII_LAN83C185_EDPWRDOWN (1 << 13) /* EDPWRDOWN */
+#define MII_LAN87XX_AUTODONE    (1 << 12) /* AUTODONE */
 #define MII_LAN83C185_ENERGYON  (1 << 1)  /* ENERGYON */
 
 #define MII_LAN83C185_MODE_MASK      0xE0
-- 
2.20.1