netdev - Re: [PATCH net-next v4 2/8] i2c: designware: Add driver support for Wangxun 10Gb NIC

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Message-ID: <20230425140859.q23mhtsk5zoc2t3d@intel.intel>
Date:   Tue, 25 Apr 2023 16:08:59 +0200
From:   Andi Shyti <andi.shyti@...nel.org>
To:     Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Cc:     Jiawen Wu <jiawenwu@...stnetic.com>, netdev@...r.kernel.org,
        andrew@...n.ch, linux@...linux.org.uk,
        jarkko.nikula@...ux.intel.com, olteanv@...il.com,
        hkallweit1@...il.com, linux-i2c@...r.kernel.org,
        linux-gpio@...r.kernel.org, mengyuanlou@...-swift.com
Subject: Re: [PATCH net-next v4 2/8] i2c: designware: Add driver support for
 Wangxun 10Gb NIC

Hi Andy,

[...]

> >  #define MODEL_MSCC_OCELOT			BIT(8)
> >  #define MODEL_BAIKAL_BT1			BIT(9)
> >  #define MODEL_AMD_NAVI_GPU			BIT(10)
> > +#define MODEL_WANGXUN_SP			BIT(11)
> >  #define MODEL_MASK				GENMASK(11, 8)
> 
> Yeah, maybe next one will need to transform this from bitfield to plain number.

You mean this?

-#define ACCESS_INTR_MASK                       BIT(0)
-#define ACCESS_NO_IRQ_SUSPEND                  BIT(1)
-#define ARBITRATION_SEMAPHORE                  BIT(2)
-
-#define MODEL_MSCC_OCELOT                      BIT(8)
-#define MODEL_BAIKAL_BT1                       BIT(9)
-#define MODEL_AMD_NAVI_GPU                     BIT(10)
-#define MODEL_MASK                             GENMASK(11, 8)
+#define ACCESS_INTR_MASK                       0x00
+#define ACCESS_NO_IRQ_SUSPEND                  0x01
+#define ARBITRATION_SEMAPHORE                  0x02
+
+#define MODEL_MSCC_OCELOT                      0x08
+#define MODEL_BAIKAL_BT1                       0x09
+#define MODEL_AMD_NAVI_GPU                     0x0a
+#define MODEL_MASK                             0x78

I actually like more bitfield to plain numbers.

Andi