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Message-ID: <20230525144359.0cb16996@pc-7.home>
Date: Thu, 25 May 2023 14:43:59 +0200
From: Maxime Chevallier <maxime.chevallier@...tlin.com>
To: Simon Horman <simon.horman@...igine.com>
Cc: Mark Brown <broonie@...nel.org>, davem@...emloft.net,
netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
alexis.lothore@...tlin.com, thomas.petazzoni@...tlin.com, Andrew Lunn
<andrew@...n.ch>, Jakub Kicinski <kuba@...nel.org>, Eric Dumazet
<edumazet@...gle.com>, Paolo Abeni <pabeni@...hat.com>, Florian Fainelli
<f.fainelli@...il.com>, Heiner Kallweit <hkallweit1@...il.com>, Russell
King <linux@...linux.org.uk>, Vladimir Oltean <vladimir.oltean@....com>,
Ioana Ciornei <ioana.ciornei@....com>,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org, Maxime Coquelin
<mcoquelin.stm32@...il.com>, Jose Abreu <joabreu@...opsys.com>, Alexandre
Torgue <alexandre.torgue@...s.st.com>, Giuseppe Cavallaro
<peppe.cavallaro@...com>
Subject: Re: [PATCH net-next v2 1/4] net: mdio: Introduce a regmap-based
mdio driver
Hello Simon,
On Thu, 25 May 2023 13:02:39 +0200
Simon Horman <simon.horman@...igine.com> wrote:
> On Thu, May 25, 2023 at 12:11:23PM +0200, Maxime Chevallier wrote:
> > There exists several examples today of devices that embed an
> > ethernet PHY or PCS directly inside an SoC. In this situation,
> > either the device is controlled through a vendor-specific register
> > set, or sometimes exposes the standard 802.3 registers that are
> > typically accessed over MDIO.
> >
> > As phylib and phylink are designed to use mdiodevices, this driver
> > allows creating a virtual MDIO bus, that translates mdiodev register
> > accesses to regmap accesses.
> >
> > The reason we use regmap is because there are at least 3 such
> > devices known today, 2 of them are Altera TSE PCS's, memory-mapped,
> > exposed with a 4-byte stride in stmmac's dwmac-socfpga variant, and
> > a 2-byte stride in altera-tse. The other one
> > (nxp,sja1110-base-tx-mdio) is exposed over SPI.
> >
> > Signed-off-by: Maxime Chevallier <maxime.chevallier@...tlin.com>
>
> ...
>
> > +struct mii_bus *devm_mdio_regmap_register(struct device *dev,
> > + const struct
> > mdio_regmap_config *config) +{
> > + struct mdio_regmap_config *mrc;
> > + struct mii_bus *mii;
> > + int rc;
> > +
> > + if (!config->parent)
> > + return ERR_PTR(-EINVAL);
> > +
> > + mii = devm_mdiobus_alloc_size(config->parent,
> > sizeof(*mrc));
> > + if (!mii)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + mrc = mii->priv;
> > + memcpy(mrc, config, sizeof(*mrc));
> > +
> > + mrc->regmap = config->regmap;
> > + mrc->valid_addr = config->valid_addr;
> > +
> > + mii->name = DRV_NAME;
> > + strscpy(mii->id, config->name, MII_BUS_ID_SIZE);
> > + mii->parent = config->parent;
> > + mii->read = mdio_regmap_read_c22;
> > + mii->write = mdio_regmap_write_c22;
> > +
> > + if (config->autoscan)
> > + mii->phy_mask = ~BIT(config->valid_addr);
> > + else
> > + mii->phy_mask = ~0UL;
>
> Hi Maxime,
>
> phy_mask is a u32.
> But 0UL may be either 32 or 64 bits wide.
Right
> I think a better approach would be to use U32_MAX.
I guess ~0 would also work, and this would also align with what
fixed-phy and sfp do for their internal MDIO bus.
I'll fix that for next revision
Thanks,
Maxime
> > +
> > + rc = devm_mdiobus_register(dev, mii);
> > + if (rc) {
> > + dev_err(config->parent, "Cannot register MDIO
> > bus![%s] (%d)\n", mii->id, rc);
> > + return ERR_PTR(rc);
> > + }
> > +
> > + return mii;
> > +}
> > +EXPORT_SYMBOL_GPL(devm_mdio_regmap_register);
> > +
> > +MODULE_DESCRIPTION("MDIO API over regmap");
> > +MODULE_AUTHOR("Maxime Chevallier <maxime.chevallier@...tlin.com>");
> > +MODULE_LICENSE("GPL");
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