netdev - Re: [PATCH net-next 1/6] platform/x86: intel_pmc_core: Add IPC mailbox accessor function and add SoC register access

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Message-ID: <ZJRdllrXB4bi7oOQ@corigine.com>
Date: Thu, 22 Jun 2023 16:41:26 +0200
From: Simon Horman <simon.horman@...igine.com>
To: Choong Yong Liang <yong.liang.choong@...ux.intel.com>
Cc: Rajneesh Bhardwaj <irenic.rajneesh@...il.com>,
	David E Box <david.e.box@...el.com>,
	Hans de Goede <hdegoede@...hat.com>,
	Mark Gross <markgross@...nel.org>,
	Jose Abreu <Jose.Abreu@...opsys.com>, Andrew Lunn <andrew@...n.ch>,
	Heiner Kallweit <hkallweit1@...il.com>,
	Russell King <linux@...linux.org.uk>,
	"David S . Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Marek Behún <kabel@...nel.org>,
	Jean Delvare <jdelvare@...e.com>,
	Guenter Roeck <linux@...ck-us.net>,
	Giuseppe Cavallaro <peppe.cavallaro@...com>,
	Alexandre Torgue <alexandre.torgue@...s.st.com>,
	Jose Abreu <joabreu@...opsys.com>,
	Maxime Coquelin <mcoquelin.stm32@...il.com>,
	Richard Cochran <richardcochran@...il.com>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	Alexei Starovoitov <ast@...nel.org>,
	Daniel Borkmann <daniel@...earbox.net>,
	Jesper Dangaard Brouer <hawk@...nel.org>,
	John Fastabend <john.fastabend@...il.com>,
	Wong Vee Khee <veekhee@...le.com>,
	Jon Hunter <jonathanh@...dia.com>,
	Jesse Brandeburg <jesse.brandeburg@...el.com>,
	Revanth Kumar Uppala <ruppala@...dia.com>,
	Shenwei Wang <shenwei.wang@....com>,
	Andrey Konovalov <andrey.konovalov@...aro.org>,
	Jochen Henneberg <jh@...neberg-systemdesign.com>,
	netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-stm32@...md-mailman.stormreply.com,
	linux-arm-kernel@...ts.infradead.org,
	platform-driver-x86@...r.kernel.org, linux-hwmon@...r.kernel.org,
	bpf@...r.kernel.org, Voon Wei Feng <weifeng.voon@...el.com>,
	Tan@....codeaurora.org, Tee Min <tee.min.tan@...ux.intel.com>,
	Michael Sit Wei Hong <michael.wei.hong.sit@...el.com>,
	Lai Peter Jun Ann <jun.ann.lai@...el.com>
Subject: Re: [PATCH net-next 1/6] platform/x86: intel_pmc_core: Add IPC
 mailbox accessor function and add SoC register access

On Thu, Jun 22, 2023 at 12:19:00PM +0800, Choong Yong Liang wrote:
> From: "David E. Box" <david.e.box@...ux.intel.com>
> 
> - Exports intel_pmc_core_ipc() for host access to the PMC IPC mailbox
> - Add support to use IPC command allows host to access SoC registers
> through PMC firmware that are otherwise inaccessible to the host due to
> security policies.
> 
> Signed-off-by: David E. Box <david.e.box@...ux.intel.com>
> Signed-off-by: Chao Qin <chao.qin@...el.com>
> Signed-off-by: Choong Yong Liang <yong.liang.choong@...ux.intel.com>

...

> diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
> index da6e7206d38b..0d60763c5144 100644
> --- a/drivers/platform/x86/intel/pmc/core.c
> +++ b/drivers/platform/x86/intel/pmc/core.c
> @@ -16,6 +16,7 @@
>  #include <linux/delay.h>
>  #include <linux/dmi.h>
>  #include <linux/io.h>
> +#include <linux/intel_pmc_core.h>
>  #include <linux/module.h>
>  #include <linux/pci.h>
>  #include <linux/slab.h>
> @@ -26,7 +27,9 @@
>  #include <asm/msr.h>
>  #include <asm/tsc.h>
>  
> -#include "core.h"
> +#define PMC_IPCS_PARAM_COUNT           7
> +
> +static const struct x86_cpu_id *pmc_cpu_id;
>  
>  /* Maximum number of modes supported by platfoms that has low power mode capability */
>  const char *pmc_lpm_modes[] = {

Hi Choong Yong Liang,

It looks like pmc_lpm_mode is used in this file and, as of this patch,
has no declaration. Should it be static?

...

> diff --git a/drivers/platform/x86/intel/pmc/core.h b/include/linux/intel_pmc_core.h
> similarity index 95%
> rename from drivers/platform/x86/intel/pmc/core.h
> rename to include/linux/intel_pmc_core.h
> index 9ca9b9746719..82810e8b92a2 100644
> --- a/drivers/platform/x86/intel/pmc/core.h
> +++ b/include/linux/intel_pmc_core.h
> @@ -250,7 +250,16 @@ enum ppfear_regs {
>  #define MTL_LPM_STATUS_OFFSET			0x1700
>  #define MTL_LPM_LIVE_STATUS_OFFSET		0x175C
>  
> -extern const char *pmc_lpm_modes[];
> +#define IPC_SOC_REGISTER_ACCESS			0xAA
> +#define IPC_SOC_SUB_CMD_READ			0x00
> +#define IPC_SOC_SUB_CMD_WRITE			0x01
> +
> +struct pmc_ipc_cmd {
> +	u32 cmd;
> +	u32 sub_cmd;
> +	u32 size;
> +	u32 wbuf[4];
> +};
>  
>  struct pmc_bit_map {
>  	const char *name;

...